| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [AMDGPU] Add subtarget features for SDWA/DPP | Sam Kolton | 2017-01-20 | 1 | -3/+1 |
| * | [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate... | Sam Kolton | 2017-01-11 | 1 | -2/+2 |
| * | AMDGPU: Fix missing 16-bit cmpx instructions | Matt Arsenault | 2016-12-22 | 1 | -0/+39 |
| * | AMDGPU: Use i16 comparison instructions | Matt Arsenault | 2016-12-22 | 1 | -2/+42 |
| * | [AMDGPU] Add pseudo SDWA instructions | Sam Kolton | 2016-12-22 | 1 | -24/+38 |
| * | [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa | Sam Kolton | 2016-12-22 | 1 | -0/+5 |
| * | AMDGPU: Fix missing commute table entries for cmpx | Matt Arsenault | 2016-12-22 | 1 | -4/+4 |
| * | [AMDGPU] Add f16 support (VI+) | Konstantin Zhuravlyov | 2016-11-13 | 1 | -140/+230 |
| * | AMDGPU: Use unsigned compare for eq/ne | Matt Arsenault | 2016-09-30 | 1 | -8/+8 |
| * | [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions | Valery Pykhtin | 2016-09-23 | 1 | -29/+21 |
| * | [AMDGPU] Refactor VOPC instruction TD definitions | Valery Pykhtin | 2016-09-19 | 1 | -0/+964 |

