bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[AMDGPU] Add intrinsics for alignbit and alignbyte instructions	Stanislav Mekhanoshin	2017-06-09	1	-2/+2
*	[AMDGPU] Force qsads instrs to use different dest register than source registers	Mark Searles	2017-06-08	1	-0/+5
*	[AMDGPU] V_DIV_FIXUP_F16 is not a commutable operation	Stanislav Mekhanoshin	2017-06-03	1	-1/+2
*	[AMDGPU] SDWA: Add assembler support for GFX9	Sam Kolton	2017-05-23	1	-4/+5
*	AMDGPU: Fix min3/max3 combines for f16/i16	Matt Arsenault	2017-05-17	1	-1/+19
*	[AMDGPU][MC] Removed V_MQSAD_U16_U8	Dmitry Preobrazhensky	2017-05-15	1	-3/+0
*	[AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)	Dmitry Preobrazhensky	2017-04-12	1	-0/+4
*	[AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI	Dmitry Preobrazhensky	2017-04-12	1	-1/+1
*	[AMDGPU][MC] Fix for Bug 28204 + LIT tests	Dmitry Preobrazhensky	2017-03-22	1	-8/+22
*	AMDGPU: Add definition for v_xad_u32	Matt Arsenault	2017-02-28	1	-0/+2
*	AMDGPU: Use v_med3_{f16\|i16\|u16}	Matt Arsenault	2017-02-27	1	-4/+12
*	AMDGPU: Add some of the new gfx9 VOP3 instructions	Matt Arsenault	2017-02-27	1	-0/+12
*	AMDGPU: Add VOP3P instruction format	Matt Arsenault	2017-02-27	1	-0/+26
*	AMDGPU: Remove modifiers from v_div_scale_*	Matt Arsenault	2017-01-19	1	-1/+5
*	[AMDGPU] Handle f16 select{_cc}	Konstantin Zhuravlyov	2016-11-16	1	-5/+0
*	AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*	Matt Arsenault	2016-11-15	1	-0/+2
*	[AMDGPU] Add f16 support (VI+)	Konstantin Zhuravlyov	2016-11-13	1	-4/+18
*	AMDGPU: Add VI i16 support	Tom Stellard	2016-11-10	1	-0/+32
*	Revert "AMDGPU: Add VI i16 support"	Tom Stellard	2016-11-04	1	-32/+0
*	AMDGPU: Add VI i16 support	Tom Stellard	2016-11-03	1	-0/+32
*	[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions	Valery Pykhtin	2016-09-23	1	-15/+15
*	[AMDGPU] Refactor VOP3 instruction TD definitions	Valery Pykhtin	2016-09-20	1	-0/+404