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path: root/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
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* Add optimization bisect opt-in calls for AMDGPU passesAndrew Kaylor2016-04-251-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D19450 llvm-svn: 267485
* AMDGPU/SI: Optimize adjacent s_nop instructionsMatt Arsenault2016-04-251-0/+27
| | | | | | | | | | | | Use the operand for how long to wait. This is somewhat distasteful, since it would be better to just emit s_nop with the right argument in the first place. This would require changing TII::insertNoop to emit N operands, which would be easy. Slightly more problematic is the post-RA scheduler and hazard recognizer represent nops as a single null node, and would require inventing another way of representing N nops. llvm-svn: 267456
* AMDGPU: Use s_addk_i32 / s_mulk_i32Matt Arsenault2016-04-161-12/+45
| | | | llvm-svn: 266506
* AMDGPU: Materialize sign bits with bfrevMatt Arsenault2016-03-111-0/+24
| | | | | | | If a constant is the same as the reverse of an inline immediate, this is 4 bytes smaller than having to embed a 32-bit literal. llvm-svn: 263201
* AMDGPU: Simplify boolean conditional return statementsMatt Arsenault2016-03-021-4/+1
| | | | | | Patch by Richard Thomson llvm-svn: 262536
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-2/+2
| | | | | | | | | | | | | | Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler. Reviewers: vpykhtin, tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, nhaustov Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D16920 llvm-svn: 260986
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-2/+1
| | | | llvm-svn: 250797
* AMDGPU: Simplify debug printingMatt Arsenault2015-09-101-1/+1
| | | | llvm-svn: 247345
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-081-2/+11
| | | | llvm-svn: 244380
* AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault2015-08-081-11/+32
| | | | llvm-svn: 244379
* AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructionsTom Stellard2015-07-141-6/+27
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11061 llvm-svn: 242146
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-131-2/+14
| | | | | | | | | The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038
* AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with ↵Tom Stellard2015-07-091-1/+1
| | | | | | | | | one use This is convered by existing testcases and will be exposed by a future commit. llvm-svn: 241817
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+272
llvm-svn: 239657
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