summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU: Use existing function to check for VGPRsMatt Arsenault2018-07-201-16/+7
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-1/+1
* AMDGPU: Remove AMDGPUMCInstLower.hTom Stellard2018-05-251-1/+0
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+2
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-0/+1
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-131-1/+1
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-241-1/+2
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* AMDGPU: Allow SIShrinkInstructions to fold FrameIndexesMatt Arsenault2017-07-101-0/+4
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-24/+33
* AMDGPU: Remove unnecessary check for constant operandsMatt Arsenault2017-07-101-5/+0
* AMDGPU: Minor cleanup of shrinking logicMatt Arsenault2017-07-061-8/+4
* [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32Stanislav Mekhanoshin2017-06-201-0/+2
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-4/+4
* AMDGPU: Fix shrinking of addc/subb.Matt Arsenault2017-01-111-7/+25
* AMDGPU: Fix breaking VOP3 v_add_i32sMatt Arsenault2017-01-111-1/+11
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-8/+11
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-0/+1
* AMDGPU: Use brev for materializing SGPR constantsMatt Arsenault2016-11-011-11/+29
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
* AMDGPU: Use unsigned compare for eq/neMatt Arsenault2016-09-301-5/+5
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-161-0/+64
* Revert "AMDGPU: Use SOPK compare instructions"Matt Arsenault2016-09-141-62/+0
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-141-0/+62
* AMDGPU: Fix immediate folding logic when shrinking instructionsMatt Arsenault2016-09-091-8/+2
* AMDGPU: Try to commute when selecting s_addk_i32/s_mulk_i32Matt Arsenault2016-09-081-9/+14
* AMDGPU: Fix adding duplicate implicit exec usesMatt Arsenault2016-09-031-1/+15
* AMDGPU/SI: Improve register allocation hints for sopk instructionsTom Stellard2016-08-291-0/+1
* AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault2016-07-191-1/+5
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-2/+2
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-2/+3
* AMDGPU: Preserve undef flag on vcc when shrinking v_cndmask_b32Matt Arsenault2016-06-201-16/+13
* AMDGPU: Properly initialize SIShrinkInstructionsMatt Arsenault2016-06-091-8/+2
* Add optimization bisect opt-in calls for AMDGPU passesAndrew Kaylor2016-04-251-0/+3
* AMDGPU/SI: Optimize adjacent s_nop instructionsMatt Arsenault2016-04-251-0/+27
* AMDGPU: Use s_addk_i32 / s_mulk_i32Matt Arsenault2016-04-161-12/+45
* AMDGPU: Materialize sign bits with bfrevMatt Arsenault2016-03-111-0/+24
* AMDGPU: Simplify boolean conditional return statementsMatt Arsenault2016-03-021-4/+1
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-2/+2
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-2/+1
* AMDGPU: Simplify debug printingMatt Arsenault2015-09-101-1/+1
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-081-2/+11
* AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault2015-08-081-11/+32
* AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructionsTom Stellard2015-07-141-6/+27
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-131-2/+14
* AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one...Tom Stellard2015-07-091-1/+1
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+272
OpenPOWER on IntegriCloud