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* [AMDGPU] Update SI scheduler colorHighLatenciesGroupsValery Pykhtin2017-03-281-22/+99
| | | | | | | | | | Depends on rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30152 llvm-svn: 298902
* [AMDGPU] SISched: Detect dependency types between blocksValery Pykhtin2017-03-271-23/+29
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30153 llvm-svn: 298872
* [AMDGPU] SISched: Update colorEndsAccordingToDependenciesValery Pykhtin2017-03-271-0/+14
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30150 llvm-svn: 298861
* [AMDGPU] Fix SI scheduler LiveOut Refcount issueValery Pykhtin2017-03-271-0/+18
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30145 llvm-svn: 298857
* [AMDGPU] Don't enforce constexpr, there are still old standard libraries ↵Benjamin Kramer2017-03-241-4/+4
| | | | | | around that don't have a constexpr std::pair. llvm-svn: 298719
* [AMDGPU] Remove double map lookups in SI schedulerValery Pykhtin2017-03-241-25/+8
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30382 llvm-svn: 298718
* [AMDGPU] Fix SGPR usage count in SI schedulerValery Pykhtin2017-03-241-2/+2
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30149 llvm-svn: 298710
* [AMDGPU] Add a new line after a debug messageValery Pykhtin2017-03-241-0/+1
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30146 llvm-svn: 298708
* Don't build up std::vectors with constant sizes when an array suffices.Benjamin Kramer2017-03-241-2/+6
| | | | | | NFC. llvm-svn: 298701
* AMDGPU: Fixed '!NodePtr->isKnownSentinel()' assertMatt Arsenault2016-12-221-17/+4
| | | | | | | | Caused by dereferencing end iterator when trying to const cast the iterator. Patch by Martin Sherburn llvm-svn: 290347
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-121-15/+25
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* Fix spelling mistakes in AMDGPU target comments. NFC.Simon Pilgrim2016-11-181-5/+5
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287333
* AMDGPU/SI: Use a better method for determining the largest pressure setsTom Stellard2016-08-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: There are a few different sgpr pressure sets, but we only care about the one which covers all of the sgprs. We were using hard-coded register pressure set names to determine the reg set id for the biggest sgpr set. However, we were using the wrong name, and this method is pretty fragile, since the reg pressure set names may change. The new method just looks for the pressure set that contains the most reg units and sets that set as our SGPR pressure set. We've also adopted the same technique for determining our VGPR pressure set. Reviewers: arsenm Subscribers: MatzeB, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D23687 llvm-svn: 279867
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-2/+1
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* AMDGPU: Prune includesMatt Arsenault2016-08-111-4/+0
| | | | llvm-svn: 278391
* AMDGPU/SI: Fix SI scheduler refcount issueMatt Arsenault2016-07-191-0/+3
| | | | | | | | | Without this fix, releaseSuccessors when InOrOutBlock is false could release SUs outside the schedule BasicBlock. Patch by Axel Davy llvm-svn: 275935
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
| | | | | | | | | | Enable testing different scheduling variants if sgpr usage is very high. It was previously disabled because of a bug in handleMove, but it has been fixed since. Patch by Axel Davy llvm-svn: 274372
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-1/+1
| | | | | | | | | Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. llvm-svn: 273652
* AMDGPU/SI: Use common topological sort algorithm in SIScheduleDAGMITom Stellard2016-06-091-64/+3
| | | | | | | | | | Reviewers: arsenm, axeldavy Subscribers: MatzeB, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19823 llvm-svn: 272346
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-271-12/+6
| | | | | | | Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
* AMDGPU/SI: Use range loops to simplify some code in the SI SchedulerTom Stellard2016-05-031-18/+18
| | | | | | | | | | Reviewers: arsenm, axeldavy Subscribers: MatzeB, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19822 llvm-svn: 268396
* Fix a couple assertions that can never fire because they just contained the ↵Craig Topper2016-04-241-1/+1
| | | | | | text string which always evaluates to true. Add a ! so they'll evaluate to false. llvm-svn: 267312
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-1/+2
| | | | | | http://reviews.llvm.org/D17967 llvm-svn: 263021
* CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | These parameters aren't expected to be null, so take them by reference. llvm-svn: 262151
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-271-4/+4
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* RegisterPressure: Make liveness tracking subregister awareMatthias Braun2016-01-201-4/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D14968 llvm-svn: 258258
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-0/+1968
Summary: It is off by default, but can be used with --misched=si Patch by: Axel Davy Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: nhaehnle, solenskiner, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D11885 llvm-svn: 257609
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