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path: root/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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* AMDGPU/SILoadStoreOptimillzer: Refactor CombineInfo structTom Stellard2019-12-171-241/+216
* AMDGPU/SILoadStoreOptimizer: Simplify functionTom Stellard2019-12-121-62/+50
* [AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/storesPiotr Sobczak2019-11-201-7/+268
* [AMDGPU] Keep consistent check of legal addressing mode.Michael Liao2019-11-201-1/+3
* AMDGPU/SILoadStoreOptimizer: fix a likely bug introduced recentlyNicolai Hähnle2019-11-161-2/+2
* Sink all InitializePasses.h includesReid Kleckner2019-11-131-0/+1
* [SILoadStoreOptimizer] Fixed typo. NFCI.Dávid Bolvanský2019-11-031-1/+1
* [AMDGPU] Extend the SI Load/Store optimizerPiotr Sobczak2019-10-161-13/+174
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-101-1/+1
* AMDGPU: Relax register classes usedMatt Arsenault2019-10-091-2/+2
* [AMDGPU][SILoadStoreOptimizer] NFC: Refactor codePiotr Sobczak2019-10-041-120/+80
* AMDGPU/SILoadStoreOptimizer: Optimize scanning for mergeable instructionsTom Stellard2019-10-031-82/+185
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-0/+8
* AMDGPU/SILoadStoreOptimizer: Add helper functions for working with CombineInfoTom Stellard2019-10-011-205/+244
* AMDGPU/SILoadStoreOptimizer: Add const to more functionsTom Stellard2019-09-191-12/+12
* [AMDGPU] Enable constant offset promotion to immediate operand for VMEM storesValery Pykhtin2019-09-061-4/+5
* AMDGPU: Disambiguate v3f16 format in load/store tablesMatt Arsenault2019-08-181-1/+3
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-14/+14
* AMDGPU/LoadStoreOptimizer: Set the correct offset whem merging MMOsTom Stellard2019-08-051-1/+6
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-4/+3
* AMDGPU/SILoadStoreOptimizer: Make some functions constTom Stellard2019-08-011-6/+6
* AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructionsTom Stellard2019-07-291-3/+38
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-3/+4
* [AMDGPU] detect WaW hazards when moving/merging load/store instructionsRhys Perry2019-05-171-0/+1
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-4/+11
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-4/+8
* AMDGPU: Use MachineInstr::mayAlias to replace areMemAccessesTriviallyDisjoint...Changpeng Fang2019-02-181-10/+8
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Fix dwordx3/southern-islands failures.Neil Henning2019-01-101-4/+5
* [AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWi...Farhana Aleen2018-12-181-2/+0
* Fix -Wunused-variable warning. NFCI.Simon Pilgrim2018-12-151-0/+4
* [SILoadStoreOptimizer] Use std::abs to avoid truncation.Florian Hahn2018-12-151-2/+2
* [AMDGPU] Promote constant offset to the immediate by finding a new base with ...Farhana Aleen2018-12-141-0/+361
* [AMDGPU] Extend the SI Load/Store optimizer to combine more things.Neil Henning2018-12-121-238/+442
* [AMDGPU] Fix ds combine with subregsStanislav Mekhanoshin2018-09-251-14/+18
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-22/+20
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-2/+2
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-3/+3
* AMDGPU: Track physreg uses in SILoadStoreOptimizerNicolai Haehnle2018-02-231-32/+32
* AMDGPU: Do not combine loads/store across physreg defsNicolai Haehnle2018-02-211-1/+19
* AMDGPU: Fix incorrect reordering when inline asm defines LDS addressMatt Arsenault2018-02-081-3/+4
* AMDGPU: Remove the s_buffer workaround for GFX9 chipsMarek Olsak2018-02-071-3/+2
* [AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32...Mark Searles2018-01-221-14/+18
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-6/+12
* AMDGPU: Select DS insts without m0 initializationMatt Arsenault2017-11-291-17/+50
* AMDGPU: Re-organize the outer loop of SILoadStoreOptimizerNicolai Haehnle2017-11-281-6/+5
* AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOp...Nicolai Haehnle2017-11-221-1/+2
* Fix "default label in switch which covers all enumeration values" warningVitaly Buka2017-11-091-2/+0
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