summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* AMDGPU: Remove unused functionMatt Arsenault2016-06-281-27/+0
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-18/+17
* AMDGPU: readlane/writelane do not read execMatt Arsenault2016-06-231-1/+24
* Reformat blank lines.NAKAMURA Takumi2016-06-201-7/+0
* Untabify.NAKAMURA Takumi2016-06-201-2/+2
* AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameI...Changpeng Fang2016-06-161-2/+2
* AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard2016-06-141-1/+1
* Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables"Tom Stellard2016-06-141-1/+1
* AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard2016-06-141-1/+1
* AMDGPU/SI: Set INDEX_STRIDE for scratch coalescingMarek Olsak2016-06-131-1/+3
* AMDGPU: Fix post-RA verifier errors with trackLivenessAfterRegAllocMatt Arsenault2016-06-131-14/+16
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-6/+5
* AMDGPU: Add function for getting instruction sizeMatt Arsenault2016-06-061-0/+49
* AMDGPU: Handle flat in getMemOpBaseRegImmOfsMatt Arsenault2016-06-021-0/+7
* AMDGPU: Fix incorrectly setting kill flag when copying register tuplesMatt Arsenault2016-06-021-1/+1
* AMDGPU: Fix verifier error when spilling SGPRsMatt Arsenault2016-05-211-0/+13
* AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault2016-05-211-0/+16
* AMDGPU: Implement ReverseBranchConditionMatt Arsenault2016-05-211-0/+7
* AMDGPU: Implement AnalyzeBranchMatt Arsenault2016-05-211-0/+109
* AMDGPU: Remove verifier check for scc live insMatt Arsenault2016-05-131-10/+0
* AMDGPU/SI: Fix bug in SIInstrInfo::insertWaitStates() uncovered by r268260Tom Stellard2016-05-021-1/+2
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-2/+36
* AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructionsTom Stellard2016-04-291-4/+0
* Fix incorrect redundant expression in target AMDGPU.Etienne Bergeron2016-04-251-1/+1
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-221-2/+1
* AMDGPU: Guard VOPC instructions against incorrect commuteNicolai Haehnle2016-04-191-3/+3
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-3/+3
* AMDGPU: Run SIFoldOperands after PeepholeOptimizerMatt Arsenault2016-04-141-0/+10
* AMDGPU/SI: Fix spilling of 96-bit registersTom Stellard2016-04-121-0/+4
* AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard2016-04-071-2/+3
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-3/+3
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
* AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructionsTom Stellard2016-03-281-8/+33
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-0/+13
* AMDGPU/SI: Clean up indentation in SIInstrInfo::getDefaultRsrcDataFormatMichel Danzer2016-03-161-3/+3
* [AMDGPU] Assembler: change v_madmk operands to have same order as mad.Nikolay Haustov2016-03-111-15/+2
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-3/+3
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-0/+2
* AMDGPU: Simplify boolean conditional return statementsMatt Arsenault2016-03-021-13/+6
* AMDGPU: Cleanup suggested in bug 23960Matt Arsenault2016-03-021-6/+3
* AMDGPU/SI: Implement DS_PERMUTE/DS_BPERMUTE Instruction Definitions and Intri...Changpeng Fang2016-03-011-0/+4
* AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointerTom Stellard2016-02-201-229/+20
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-1/+1
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-10/+59
* AMDGPU: Set element_size in private resource descriptorMatt Arsenault2016-02-121-0/+4
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+42
* AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklistTom Stellard2016-02-111-0/+2
* AMDGPU: Fix constant bus use check with subregistersMatt Arsenault2016-02-111-4/+8
* AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfoTom Stellard2016-02-051-42/+0
* AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cppTom Stellard2016-01-281-19/+11
OpenPOWER on IntegriCloud