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path: root/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
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* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-1/+1
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-15/+17
* [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev2018-04-251-64/+15
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-11/+14
* [AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev2017-12-011-15/+64
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-17/+17
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-08-081-19/+32
* [AMDGPU] Add support for Whole Wavefront ModeConnor Abbott2017-08-041-1/+2
* [AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQMConnor Abbott2017-08-041-1/+5
* AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when ...Changpeng Fang2017-08-031-3/+3
* [AMDGPU] Eliminate SGPR to VGPR copy when possibleStanislav Mekhanoshin2017-06-201-0/+30
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault2017-04-291-4/+9
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-241-9/+176
* AMDGPU : Fix common dominator of two incoming blocks terminates with uniform ...Wei Ding2017-04-121-2/+24
* AMDGPU: Fix folding reg_sequence into copy to phys regMatt Arsenault2017-04-111-0/+4
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-2/+3
* AMDGPU/SI: Don't move copies of immediates to the VALUTom Stellard2016-12-061-1/+43
* AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar br...Tom Stellard2016-11-291-8/+38
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-111-24/+44
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
* Revert "AMDGPU: Remove unused control flow intrinsic"Matt Arsenault2016-07-091-0/+1
* AMDGPU: Remove unused control flow intrinsicMatt Arsenault2016-07-081-1/+0
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-4/+3
* AMDGPU: Fix debug name of pass to better matchMatt Arsenault2016-04-211-1/+1
* AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle2016-01-071-1/+1
* AMDGPU: Initialize SIFixSGPRCopies so -print-after worksMatt Arsenault2015-11-031-6/+9
* AMDGPU: Stop assuming vreg for build_vectorMatt Arsenault2015-11-021-1/+4
* AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCEMatt Arsenault2015-11-021-23/+89
* AMDGPU: Refactor isVGPRToSGPRCopyMatt Arsenault2015-10-131-19/+48
* AMDGPU: Remove inferRegClassFromUses / inferRegClassFromDefsMatt Arsenault2015-10-071-70/+0
* AMDGPU: Remove dead codeMatt Arsenault2015-10-011-7/+4
* AMDGPU: Fix recomputing dominator tree unnecessarilyMatt Arsenault2015-09-251-0/+4
* AMDGPU: Move copy handling under switch like other instructionsMatt Arsenault2015-09-211-5/+10
* AMDGPU: Simplify debug printingMatt Arsenault2015-09-101-3/+1
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+338
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