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* AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)Jan Vesely2020-02-101-1/+6
| | | | | | | | | | | | The old version might be faster on EG (RECIP_IEEE is Trans only), but it'd need extra corner case checks. This gives correct corner case behaviour and saves a register. Fixes OCL CTS sqrt test (1-thread, scalar) on Turks. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D74017 (cherry picked from commit e6686adf8a743564f0c455c34f04752ab08cf642)
* AMDGPU: Eliminate more legacy codepred address space PatFragsMatt Arsenault2020-01-091-5/+20
| | | | These should now be limited to R600 code.
* AMDGPU: Redefine load PatFragsMatt Arsenault2019-07-161-0/+2
| | | | | | | Rewrite PatFrags using the new PatFrag address space matching in tablegen. These will now work with both SelectionDAG and GlobalISel. llvm-svn: 366234
* AMDGPU: Avoid code predicates for extload PatFragsMatt Arsenault2019-07-161-0/+26
| | | | | | | | | | Use the MemoryVT field. This will be necessary for tablegen to automatically handle patterns for GlobalISel. Doesn't handle the d16 lo/hi patterns. Those are a special case since it involvess the custom node type. llvm-svn: 366168
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-4/+4
| | | | llvm-svn: 341165
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-64/+29
| | | | | | | | | | | | | | | | | | | | | Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
* AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.tdTom Stellard2018-06-011-1/+0
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47487 llvm-svn: 333720
* AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard2018-05-241-8/+0
| | | | | | | | | | | | | | | | Summary: We don't generate AMDGPUISD::CLAMP for R600 now that llvm.AMDGPU.clamp is gone. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D47181 llvm-svn: 333153
* AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsicTom Stellard2018-04-241-5/+0
| | | | | | | | | | | | | | Summary: This is no longer used by mesa since its 18.0.0 release. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D45988 llvm-svn: 330775
* AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.tdTom Stellard2018-01-291-0/+1
| | | | | | | | | | | | | | Summary: This is only used by R600. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D37114 llvm-svn: 323709
* AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely2017-12-041-1/+4
| | | | | | | | | Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-37/+38
| | | | | | | | | | | | | | These are problematic because they apply to everything, and can easily clobber whatever more specific predicate you are trying to add to a function. Currently instructions use SubtargetPredicate/PredicateControl to apply this to patterns applied to an instruction definition, but not to free standing Pats. Add a wrapper around Pat so the special PredicateControls requirements can be appended to the final predicate list like how Mips does it. llvm-svn: 314742
* AMDGPU: Move r600 only code into r600 only td fileMatt Arsenault2017-09-201-0/+54
| | | | llvm-svn: 313719
* AMDGPU: Remove deadcode from AMDGPUInstPrinterTom Stellard2017-07-291-3/+1
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D36034 llvm-svn: 309477
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-4/+4
| | | | | | | | | | | | | | | | | | As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
* AMDGPU: Remove llvm.AMDGPU.cube intrinsicMatt Arsenault2017-02-161-1/+1
| | | | llvm-svn: 295359
* AMDGPU/R600: Serialize vector trunc stores to private ASJan Vesely2017-01-201-0/+14
| | | | | | | | | | | Add DUMMY_CHAIN SDNode to denote stores of interest Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=28915 Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=30411 Differential Revision: https://reviews.llvm.org/D27964 llvm-svn: 292651
* AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodesJan Vesely2017-01-061-0/+11
| | | | | | | | This will make transition to SCRATCH_MEMORY easier Differential Revision: https://reviews.llvm.org/D24746 llvm-svn: 291279
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-051-6/+1
| | | | | | | | | | | | | | | Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. llvm-svn: 288695
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-071-14/+0
| | | | llvm-svn: 283515
* AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault2016-08-271-6/+15
| | | | llvm-svn: 279902
* AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely2016-08-151-8/+8
| | | | | | | | | Use patterns instead of multiple instructions Add buffer id to asm string https://reviews.llvm.org/D22650 llvm-svn: 278749
* AMDGPU: Fix TargetPrefix for remaining r600 intrinsicsMatt Arsenault2016-07-151-4/+4
| | | | llvm-svn: 275619
* AMDGPU: Remove legacy rsq.clamped intrinsicMatt Arsenault2016-07-151-2/+1
| | | | | | | | Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining. Also fix mismatch with non-IEEE rsq selecting to IEEE rsq. llvm-svn: 275617
* AMDGPU/R600: Delete/rename intrinsics no longer used by mesaMatt Arsenault2016-07-141-7/+2
| | | | | | Use the replacement pass to update the tests, and delete old names. llvm-svn: 275375
* AMDGPU/R600: Remove intrinsics with no tests and no usersMatt Arsenault2016-07-141-27/+3
| | | | | | Mesa removed this path, so nothing is using these anymore. llvm-svn: 275372
* AMDGPU/R600: Add implicitarg.ptr intrinsicJan Vesely2016-07-101-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D21622 llvm-svn: 275024
* AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loadsTom Stellard2016-07-051-0/+25
| | | | | | | | | This moves of the r600 logic out of isGlobalLoad() and into the TableGen files. Differential Revision: http://reviews.llvm.org/D21710 llvm-svn: 274527
* AMDGPU/R600: Add indentation to VTX and TEX fetch asm stringsJan Vesely2016-07-041-2/+2
| | | | | | | | These are printed as part of Fetch clauses. Differential Revision: http://reviews.llvm.org/D21730 llvm-svn: 274517
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-2/+2
| | | | | | | | | Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. llvm-svn: 273652
* AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault2016-06-221-2/+3
| | | | | | | | | | | | | The main sin this was committing was using terminator instructions in the middle of the block, and then not updating the block successors / predecessors. Split the blocks up to avoid this and introduce new pseudo instructions for branches taken with exec masking. Also use a pseudo instead of emitting s_endpgm and erasing it in the special case of a non-void return. llvm-svn: 273467
* AMDGPU/R600: Implement memory loads from constant ASJan Vesely2016-05-131-0/+7
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19792 llvm-svn: 269479
* AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault2016-02-131-1/+1
| | | | | | Also fixes missing f32 test. llvm-svn: 260780
* AMDGPU: Remove 24-bit intrinsicsMatt Arsenault2016-01-291-6/+0
| | | | | | | The known bit matching code seems to work reasonably well, so these shouldn't really be needed. llvm-svn: 259180
* AMDGPU: Remove more unused intrinsicsMatt Arsenault2016-01-231-7/+3
| | | | | | Replace tests with lrp with basic IR expansion llvm-svn: 258612
* AMDGPU: Remove random TGSI intrinsicMatt Arsenault2016-01-221-7/+0
| | | | | | I don't think this was ever used. llvm-svn: 258514
* AMDGPU: Remove AMDGPU.fract intrinsicMatt Arsenault2016-01-221-0/+1
| | | | | | | Mesa doesn't use this, and this is pattern matched already from fsub x, (ffloor x) llvm-svn: 258513
* Fix typos.Bruce Mitchener2015-09-121-1/+1
| | | | | | | | | | Summary: This fixes a variety of typos in docs, code and headers. Subscribers: jholewinski, sanjoy, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12626 llvm-svn: 247495
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+1744
| | | | llvm-svn: 239657
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-1322/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+1322
llvm-svn: 160270
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