summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/MCTargetDesc
Commit message (Collapse)AuthorAgeFilesLines
...
* AMDGPU: Fix emitting encoded callsMatt Arsenault2017-08-021-1/+1
| | | | | | | | | | This was failing on out of bounds access to the extra operands on the s_swappc_b64 beyond those in the instruction definition. This was working, but somehow regressed within the past few weeks, although I don't see any obvious commit. llvm-svn: 309782
* Fully fix the movw/movt addend.Rafael Espindola2017-07-111-2/+2
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* AMDGPU: Whitespace fixesMatt Arsenault2017-06-261-1/+1
| | | | llvm-svn: 306265
* Remove a processFixupValue hack.Rafael Espindola2017-06-242-35/+32
| | | | | | | | | | | The intention of processFixupValue is not to redefine the semantics of MCExpr. It is odd enough that a expression lowers to a PCRel MCExpr or not depending on what it looks like. At least it is a local hack now. I left a fix for anyone trying to figure out what producers should be producing a different expression. llvm-svn: 306200
* Remove redundant argument.Rafael Espindola2017-06-241-2/+2
| | | | llvm-svn: 306189
* Move Value adjustment to applyFixup. NFC.Rafael Espindola2017-06-231-2/+1
| | | | llvm-svn: 306178
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-2/+4
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* Use a MutableArrayRef. NFC.Rafael Espindola2017-06-211-4/+4
| | | | llvm-svn: 305968
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-2/+0
| | | | | | | | | | See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509 Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin Differential Revision: https://reviews.llvm.org/D34360 llvm-svn: 305923
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-212-21/+21
| | | | | | | | | | | | Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9. Reviewers: dp, arsenm, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov Differential Revision: https://reviews.llvm.org/D34026 llvm-svn: 305886
* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-072-2/+2
| | | | | | | | | | | | This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
* AMDGPU/NFC: Move amdgpu code object metadata to supportKonstantin Zhuravlyov2017-06-063-617/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D31437 llvm-svn: 304812
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-064-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* AMDGPU: Remove deprecated and unused elf definitionsKonstantin Zhuravlyov2017-06-052-40/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D33689 llvm-svn: 304737
* [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodesDmitry Preobrazhensky2017-05-261-1/+1
| | | | | | | | | | See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171 Reviewers: Sam Kolton Differential Revision: https://reviews.llvm.org/D33553 llvm-svn: 304015
* [AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton2017-05-261-4/+8
| | | | | | | | | | | | Summary: Added decoder methods and tests Reviewers: vpykhtin, artem.tamazov, dp Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33545 llvm-svn: 303999
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-232-0/+54
| | | | | | | | | | | | | | | Summary: Added separate pseudo and real instruction for GFX9 SDWA instructions. Currently supports only in assembler. Depends D32493 Reviewers: vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33132 llvm-svn: 303620
* AMDGPU: Fix ValueKind code object metadata for imagesKonstantin Zhuravlyov2017-04-251-12/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D32504 llvm-svn: 301360
* AMDGPU: Set StackGrowsUp in MCAsmInfoMatt Arsenault2017-04-241-0/+1
| | | | | | Not sure what this does though. llvm-svn: 301229
* AMDGPU: Set CodePointerSize to 8 for amdgcnKonstantin Zhuravlyov2017-04-171-0/+1
| | | | llvm-svn: 300470
* [AMDGPU] set read_only access qualifier for pointersStanislav Mekhanoshin2017-04-141-3/+8
| | | | | | | | | | If a kernel's pointer argument is known to be readonly set access qualifier accordingly. This allows RT not to flush caches before dispatches. Differential Revision: https://reviews.llvm.org/D32091 llvm-svn: 300362
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+6
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* AMDGPU: Actually write nops for writeNopDataMatt Arsenault2017-04-081-1/+14
| | | | | | | Before this was just writing 0s, which ends up looking like a v_cndmask_b32 v0, s0, v0, vcc. Write out an encoded s_nop instead. llvm-svn: 299816
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-2/+2
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-272-11/+12
| | | | | | | | | | | | | | | | | | As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
* [AMDGPU] Rename Kind to ValueKind in metadata to be consistentKonstantin Zhuravlyov2017-03-242-2/+2
| | | | llvm-svn: 298722
* [AMDGPU] Do not emit isa info as code object metadataKonstantin Zhuravlyov2017-03-225-137/+17
| | | | | | | | - It was decided to expose this information through other means (rocr) Differential Revision: https://reviews.llvm.org/D30970 llvm-svn: 298560
* [AMDGPU] Emit kernel debug properties as code object metadataKonstantin Zhuravlyov2017-03-223-9/+110
| | | | | | Differential Revision: https://reviews.llvm.org/D30969 llvm-svn: 298558
* [AMDGPU] Emit kernel code properties as code object metadataKonstantin Zhuravlyov2017-03-225-5/+135
| | | | | | | | - These are not required for low level runtime Differential Revision: https://reviews.llvm.org/D29949 llvm-svn: 298556
* [AMDGPU] Restructure code object metadata creationKonstantin Zhuravlyov2017-03-228-555/+1080
| | | | | | | | | | | | | | | | | - Rename runtime metadata -> code object metadata - Make metadata not flow - Switch enums to use ScalarEnumerationTraits - Cleanup and move AMDGPUCodeObjectMetadata.h to AMDGPU/MCTargetDesc - Introduce in-memory representation for attributes - Code object metadata streamer - Create metadata for isa and printf during EmitStartOfAsmFile - Create metadata for kernel during EmitFunctionBodyStart - Finalize and emit metadata to .note during EmitEndOfAsmFile - Other minor improvements/bug fixes Differential Revision: https://reviews.llvm.org/D29948 llvm-svn: 298552
* [AMDGPU] Fix bug 31610Konstantin Zhuravlyov2017-03-221-3/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D31258 llvm-svn: 298551
* Rename PT_NOTE namespace name used in AMDGPUPTNote.hYaxun Liu2017-03-102-9/+10
| | | | | | | | Patch by Guansong Zhang. Differential Revision: https://reviews.llvm.org/D30750 llvm-svn: 297498
* Revert "AMDGPU: Set MCAsmInfo::PointerSize"Konstantin Zhuravlyov2017-03-071-1/+0
| | | | | | | | It breaks line tables because the patch is not complete, working on a complete one at the moment This reverts commit r294031. llvm-svn: 297118
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-4/+24
| | | | | | | | Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368
* [AMDGPU] Runtime metadata fixes:Konstantin Zhuravlyov2017-02-274-23/+65
| | | | | | | | | | | - Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it: .amdgpu_runtime_metadata { amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ... - Make IsaInfo optional, and always emit it. Differential Revision: https://reviews.llvm.org/D30349 llvm-svn: 296324
* AMDGPU: Fix trailing whitespaceMatt Arsenault2017-02-101-1/+1
| | | | llvm-svn: 294694
* [AMDGPU][NFC] Assign IsaInfo to reference variable in order to shorten long ↵Konstantin Zhuravlyov2017-02-081-16/+13
| | | | | | lines llvm-svn: 294454
* [AMDGPU] Add target information that is required by tools to metadataKonstantin Zhuravlyov2017-02-084-9/+56
| | | | | | Differential Revision: https://reviews.llvm.org/D28760#fb670e28 llvm-svn: 294449
* [AMDGPU] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-031-5/+9
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294067
* AMDGPU: Set MCAsmInfo::PointerSizeMatt Arsenault2017-02-031-0/+1
| | | | llvm-svn: 294031
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-021-0/+2
| | | | | | | | | | | The operand types were defined to fit the fp16_to_fp node, which has the half as an integer type. v_cvt_f32_f16 does support source modifiers, so change this to have an FP type and modifiers. For targets without legal f16, this requires recognizing the bit operations and trying to produce them. llvm-svn: 293857
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-201-10/+19
| | | | | | other minor fixes (NFC). llvm-svn: 292623
* Apply clang-tidy's performance-unnecessary-value-param to LLVM.Benjamin Kramer2017-01-132-7/+5
| | | | | | | With some minor manual fixes for using function_ref instead of std::function. No functional change intended. llvm-svn: 291904
* Enable '-Wstring-conversion' and fix some bad asserts that it helpedChandler Carruth2016-12-231-1/+1
| | | | | | | | find. Notable is the assert in NewGVN which had no effect because of the bug. llvm-svn: 290400
* AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for ↵Sam Kolton2016-12-192-71/+95
| | | | | | | | | | | | | | | | | | | | | | | | functime metadata V2.0 Summary: Added pair of directives .hsa_code_object_metadata/.end_hsa_code_object_metadata. Between them user can put YAML string that would be directly put to the generated note. E.g.: ''' .hsa_code_object_metadata { amd.MDVersion: [ 2, 0 ] } .end_hsa_code_object_metadata ''' Based on D25046 Reviewers: vpykhtin, nhaustov, yaxunl, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, mgorny, tony-tye Differential Revision: https://reviews.llvm.org/D27619 llvm-svn: 290097
* Fix build failure due to r289674 on certain systemsYaxun Liu2016-12-141-1/+0
| | | | | | Removed a useless include which caused conflict. llvm-svn: 289700
* AMDGPU: Emit runtime metadata version 2 as YAMLYaxun Liu2016-12-145-338/+445
| | | | | | Differential Revision: https://reviews.llvm.org/D25046 llvm-svn: 289674
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-122-16/+24
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-14/+49
| | | | | | | | | | | | | | | | | | Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-193-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
OpenPOWER on IntegriCloud