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path: root/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
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* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-2/+2
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-2/+2
* AMDGPU: Cleanup local atomic node namesMatt Arsenault2017-10-231-1/+1
* Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.Wei Ding2017-10-121-1/+1
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-32/+39
* AMDGPU: Cleanup load/store PatFragsMatt Arsenault2017-09-201-5/+5
* AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault2017-03-151-1/+1
* AMDGPU: Add another BFE patternMatt Arsenault2017-02-231-1/+1
* ADMGPU/EG,CM: Implement _noret global atomicsJan Vesely2017-01-161-7/+108
* AMDGPU/EG,CM: Add fp16 conversion instructionsJan Vesely2017-01-111-1/+3
* AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault2016-08-271-0/+2
* AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely2016-08-151-87/+50
* AMDGPU/R600: Replace barrier intrinsicsMatt Arsenault2016-07-181-6/+1
* AMDGPU/R600: Add implicitarg.ptr intrinsicJan Vesely2016-07-101-5/+5
* AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loadsTom Stellard2016-07-051-20/+20
* AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)Jan Vesely2016-05-131-0/+26
* AMDGPU: Remove 24-bit intrinsicsMatt Arsenault2016-01-291-2/+0
* AMDGPU: Remove random TGSI intrinsicMatt Arsenault2016-01-221-2/+0
* AMDGPU: Pattern match ffbh pattern to instruction.Matt Arsenault2016-01-111-1/+1
* AMDGPU: Add MEM_RAT STORE_TYPED.Tom Stellard2015-10-011-0/+11
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+670
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