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* [AMDGPU] gfx1010 exp modificationsStanislav Mekhanoshin2019-05-081-1/+6
* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-10/+64
* [AMDGPU] gfx1010 constant bus limitStanislav Mekhanoshin2019-05-021-2/+32
* [AMDGPU] gfx1010 MIMG implementationStanislav Mekhanoshin2019-05-011-7/+206
* [AMDGPU] gfx1010 DS implementationStanislav Mekhanoshin2019-05-011-2/+3
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-6/+42
* Move if() to newline to stop ambiguity over whether it should be else if. NFCI.Simon Pilgrim2019-04-291-1/+2
* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-261-1/+2
* [AMDGPU] gfx1010 VOP3 and VOP3P implementationStanislav Mekhanoshin2019-04-261-0/+9
* [AMDGPU] gfx1010 VOP2 changesStanislav Mekhanoshin2019-04-261-22/+78
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-19/+52
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-241-2/+6
* [AMDGPU][MC] Parser cleanup and refactoringDmitry Preobrazhensky2019-04-241-93/+48
* [AMDGPU][MC] Corrected parsing of SP3 'neg' modifierDmitry Preobrazhensky2019-04-221-24/+58
* [AMDGPU][MC] Corrected handling of "-" before expressionsDmitry Preobrazhensky2019-04-171-38/+58
* [AMDGPU][MC] Corrected parsing of registersDmitry Preobrazhensky2019-04-171-27/+126
* AMDGPU: Fix names for generation featuresMatt Arsenault2019-04-031-1/+1
* [AMDGPU][MC] Corrected conversion rules for inlinable constants to match rule...Dmitry Preobrazhensky2019-03-291-15/+15
* [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodesDmitry Preobrazhensky2019-03-291-7/+7
* Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic retur...Dmitry Preobrazhensky2019-03-271-7/+7
* [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodesDmitry Preobrazhensky2019-03-271-7/+7
* AMDHSA: Fix COMPUTE_PGM_RSRC2.USER_SGPR calculation when parsing ISA assemblyKonstantin Zhuravlyov2019-03-201-7/+7
* [AMDGPU] Added MsgPack format PAL metadataTim Renouf2019-03-201-13/+50
* [AMDGPU] Factored PAL metadata handling out into its own classTim Renouf2019-03-201-4/+12
* [AMDGPU][MC] Corrected checks for DS offset0 rangeDmitry Preobrazhensky2019-03-201-1/+1
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+41
* [AMDGPU] Silence gcc 7 warningsStanislav Mekhanoshin2019-03-131-3/+3
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-121-0/+37
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-111-2/+3
* [AMDGPU] Mark enum types in SIDefines.h as unsignedStanislav Mekhanoshin2019-03-111-2/+2
* [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b3...Dmitry Preobrazhensky2019-03-041-44/+73
* [AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operandsDmitry Preobrazhensky2019-02-271-11/+15
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-4/+87
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-081-0/+88
* [AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and ste...Dmitry Preobrazhensky2019-02-081-0/+4
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-192-8/+6
* [AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructionsDmitry Preobrazhensky2019-01-181-0/+39
* [AMDGPU] Emit MessagePack HSA Metadata for v3 code objectScott Linder2018-12-121-7/+25
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-5/+7
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-121-20/+16
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into Targ...Ilya Biryukov2018-09-121-16/+20
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-20/+16
* [AMDGPU] Add support for a16 modifiear for gfx9Ryan Taylor2018-08-281-27/+10
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-211-10/+55
* [AMDGPU] Update assembler for HSA Code Object v3Scott Linder2018-06-211-20/+432
* AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle2018-06-211-36/+1
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-211-12/+19
* [AMDGPU][MC] Enabled parsing of relocations on VALU instructionsDmitry Preobrazhensky2018-06-131-2/+2
* [AMDGPU] Added checks for dpp_ctrl valueStanislav Mekhanoshin2018-05-081-23/+27
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-4/+6
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