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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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* [AMDGPU] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* [AMDGPU] gfx1010 GCNRegBankReassign passStanislav Mekhanoshin2019-05-011-0/+2
* [AMDGPU] gfx1010 GCNNSAReassign passStanislav Mekhanoshin2019-05-011-0/+15
* [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their...Amara Emerson2019-04-151-0/+6
* Reapply [ValueTracking] Support min/max selects in computeConstantRange()Nikita Popov2019-04-071-2/+9
* [AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin2019-04-051-0/+9
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-011-7/+5
* AMDGPU: Add additional MIR tests for exec mask optimizationsMatt Arsenault2019-03-271-3/+11
* CodeGen: Refactor regallocator command line and target selectionMatt Arsenault2019-03-191-6/+6
* [AMDGPU] Add an experimental buffer fat pointer address space.Neil Henning2019-03-181-2/+3
* AMDGPU: Partially fix default device for HSAMatt Arsenault2019-03-171-1/+2
* MIR: Allow targets to serialize MachineFunctionInfoMatt Arsenault2019-03-141-0/+73
* AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV)Aakanksha Patil2019-03-071-1/+3
* AMDGPU: Fix typoMatt Arsenault2019-02-281-1/+1
* AMDGPU: Enable function calls by defaultMatt Arsenault2019-02-281-4/+9
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-211-2/+0
* [AMDGPU] Enable DPP combiner pass by default.Valery Pykhtin2019-02-111-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard2019-01-141-0/+1
* Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-131-3/+1
* [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-121-1/+3
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-0/+9
* [Targets] Add errors for tiny and kernel codemodel on targets that don't supp...David Green2018-12-071-7/+1
* [AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by defaultValery Pykhtin2018-12-061-1/+1
* [AMDGPU]: Turn on the DPP combiner by defaultValery Pykhtin2018-12-051-1/+1
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-0/+8
* Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard2018-11-291-1/+0
* Add support for TFE/LWE in image intrinsicsDavid Stuttard2018-11-291-0/+1
* AMDGPU: Don't optimize exec masks at -O0Matt Arsenault2018-11-261-1/+2
* [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman2018-11-161-0/+2
* Allow subclassing ExternalAAMatt Arsenault2018-11-071-7/+1
* AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle2018-10-311-1/+1
* [AMDGPU] Add a pass to promote bitcast callsScott Linder2018-10-261-0/+6
* [AMDGPU] Add an AMDGPU specific atomic optimizer.Neil Henning2018-10-081-0/+12
* AMDGPU: Always run AMDGPUAlwaysInlineMatt Arsenault2018-10-031-12/+9
* AMDGPU: Expand atomicrmw nand in IRMatt Arsenault2018-10-021-0/+1
* [AMDGPU] restore r342722 which was reverted with r342743Sameer Sahasrabuddhe2018-09-251-0/+2
* revert changes from r342722Sameer Sahasrabuddhe2018-09-211-2/+0
* [AMDGPU] lower-switch in preISel as a workaround for legacy DASameer Sahasrabuddhe2018-09-211-0/+2
* AMDGPU: Stop forcing internalize at -O0Matt Arsenault2018-08-311-11/+0
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-1/+0
* run post-RA hazard recognizer pass lateMark Searles2018-07-161-3/+7
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-3/+3
* Reapply "AMDGPU: Force inlining if LDS global address is used"Matt Arsenault2018-07-101-5/+7
* Revert "AMDGPU: Force inlining if LDS global address is used"Vlad Tsyrklevich2018-07-101-7/+5
* AMDGPU: Force inlining if LDS global address is usedMatt Arsenault2018-07-091-5/+7
* [AMDGPU] Enable LICM in the BE pipelineStanislav Mekhanoshin2018-06-291-0/+1
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-0/+11
* [AMDGPU] Construct memory clauses before RAStanislav Mekhanoshin2018-05-311-0/+3
* AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTITom Stellard2018-05-301-5/+10
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