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path: root/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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* AMDGPU/GlobalISel: Convert to using RegisterMatt Arsenault2019-06-281-4/+4
| | | | llvm-svn: 364616
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-241-12/+12
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-4/+4
| | | | | | | | | Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
* AMDGPU: Consolidate some getGeneration checksMatt Arsenault2019-06-191-3/+2
| | | | | | | | This is incomplete, and ideally these would all be removed, but it's better to localize them to the subtarget first with comments about what they're for. llvm-svn: 363902
* AMDGPU/GlobalISel: Legality for integer min/maxMatt Arsenault2019-05-231-0/+23
| | | | llvm-svn: 361519
* AMDGPU/GlobalISel: Implement s64->s64 [SU]ITOFPMatt Arsenault2019-05-171-0/+37
| | | | llvm-svn: 361082
* GlobalISel: Implement lower for S64->S32 [SU]ITOFPMatt Arsenault2019-05-171-0/+1
| | | | | | | | | | | | | This is ported from the custom AMDGPU DAG implementation. I think this is a better default expansion than what the DAG currently uses, at least if the target has CTLZ. This implements the signed version in terms of the unsigned conversion, which is implemented with bit operations. SelectionDAG has several other implementations that should eventually be ported depending on what instructions are legal. llvm-svn: 361081
* AMDGPU: Fix unused variable warnings in release buildsMatt Arsenault2019-05-171-12/+9
| | | | llvm-svn: 361030
* AMDGPU/GlobalISel: Legalize G_FCEILMatt Arsenault2019-05-171-2/+35
| | | | llvm-svn: 361028
* AMDGPU/GlobalISel: Legalize G_INTRINSIC_TRUNCMatt Arsenault2019-05-171-3/+68
| | | | llvm-svn: 361027
* AMDGPU/GlobalISel: Legalize G_FRINTMatt Arsenault2019-05-171-0/+41
| | | | llvm-svn: 361026
* AMDGPU/GlobalISel: Legalize G_FCOPYSIGNMatt Arsenault2019-05-171-0/+4
| | | | llvm-svn: 361025
* AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sourcesMatt Arsenault2019-04-221-1/+3
| | | | llvm-svn: 358894
* [GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with ↵Amara Emerson2019-04-151-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constants only. Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't be degraded. This change also improves the IRTranslator so that in most places, but not all, it creates constants using the MIRBuilder directly instead of first creating a new destination vreg and then creating a constant. By doing this, the buildConstant() method can just return the vreg of an existing G_CONSTANT instead of having to create a COPY from it. I measured a 0.2% improvement in compile time and a 0.9% improvement in code size at -O0 ARM64. Compile time: Program base cse diff test-suite...ark/tramp3d-v4/tramp3d-v4.test 9.04 9.12 0.8% test-suite...Mark/mafft/pairlocalalign.test 2.68 2.66 -0.7% test-suite...-typeset/consumer-typeset.test 5.53 5.51 -0.4% test-suite :: CTMark/lencod/lencod.test 5.30 5.28 -0.3% test-suite :: CTMark/Bullet/bullet.test 25.82 25.76 -0.2% test-suite...:: CTMark/ClamAV/clamscan.test 6.92 6.90 -0.2% test-suite...TMark/7zip/7zip-benchmark.test 34.24 34.17 -0.2% test-suite :: CTMark/SPASS/SPASS.test 6.25 6.24 -0.1% test-suite...:: CTMark/sqlite3/sqlite3.test 1.66 1.66 -0.1% test-suite :: CTMark/kimwitu++/kc.test 13.61 13.60 -0.0% Geomean difference -0.2% Code size: Program base cse diff test-suite...-typeset/consumer-typeset.test 1315632 1266480 -3.7% test-suite...:: CTMark/ClamAV/clamscan.test 1313892 1297508 -1.2% test-suite :: CTMark/lencod/lencod.test 1439504 1423112 -1.1% test-suite...TMark/7zip/7zip-benchmark.test 2936980 2904172 -1.1% test-suite :: CTMark/Bullet/bullet.test 3478276 3445460 -0.9% test-suite...ark/tramp3d-v4/tramp3d-v4.test 8082868 8033492 -0.6% test-suite :: CTMark/kimwitu++/kc.test 3870380 3853972 -0.4% test-suite :: CTMark/SPASS/SPASS.test 1434904 1434896 -0.0% test-suite...Mark/mafft/pairlocalalign.test 764528 764528 0.0% test-suite...:: CTMark/sqlite3/sqlite3.test 782092 782092 0.0% Geomean difference -0.9% Differential Revision: https://reviews.llvm.org/D60580 llvm-svn: 358369
* AMDGPU/GlobalISel: Fix non-power-of-2 selectMatt Arsenault2019-04-051-0/+1
| | | | llvm-svn: 357762
* GlobalISel: Implement fewerElementsVector for phiMatt Arsenault2019-02-281-0/+1
| | | | llvm-svn: 355048
* GlobalISel: Implement moreElementsVector for phiMatt Arsenault2019-02-281-0/+1
| | | | llvm-svn: 355047
* AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizesMatt Arsenault2019-02-251-0/+2
| | | | llvm-svn: 354825
* AMDGPU/GlobalISel: Clamp max implicit_def elementsMatt Arsenault2019-02-251-1/+2
| | | | llvm-svn: 354818
* AMDGPU/GlobalISel: Make phis legalMatt Arsenault2019-02-211-0/+13
| | | | llvm-svn: 354592
* AMDGPU/GlobalISel: Fix bit count ops for non-power-of-2 typesMatt Arsenault2019-02-211-1/+3
| | | | llvm-svn: 354587
* GlobalISel: Fix fewerElementsVector for ctlz with different result typeMatt Arsenault2019-02-201-2/+2
| | | | | | Also complete the set of related operations. llvm-svn: 354480
* GlobalISel: Implement moreElementsVector for g_insert resultsMatt Arsenault2019-02-201-14/+24
| | | | llvm-svn: 354477
* GlobalISel: Implement moreElementsVector for selectMatt Arsenault2019-02-191-18/+9
| | | | llvm-svn: 354354
* GlobalISel: Implement moreElementsVector for G_EXTRACT sourceMatt Arsenault2019-02-191-0/+1
| | | | llvm-svn: 354348
* GlobalISel: Implement moreElementsVector for bit opsMatt Arsenault2019-02-191-0/+20
| | | | llvm-svn: 354345
* GlobalISel: Implement widenScalar for g_extract scalar resultsMatt Arsenault2019-02-181-2/+3
| | | | llvm-svn: 354293
* GlobalISel: Add alignment to LegalityQuery MMOsMatt Arsenault2019-02-141-9/+10
| | | | | | | This allows targets to specify the minimum alignment required for the load/store. llvm-svn: 354071
* AMDGPU/GlobalISel: Fix RegBankSelect for GEP.Matt Arsenault2019-02-141-22/+14
| | | | | | | | | | This is basically a pointer typed add, so shouldn't be any different. This was assuming everything was an SGPR, which is not true. Also cleanup legality for GEP. I don't seem to be seeing the problem the hack marking s64 as a legal pointer type the comment mentions. llvm-svn: 354067
* AMDGPU/GlobalISel: Only make f16 constants legal on f16 targetsMatt Arsenault2019-02-121-2/+9
| | | | | | We could deal with it, but there's no real point. llvm-svn: 353845
* GlobalISel: Implement moreElementsVector for implicit_defMatt Arsenault2019-02-111-1/+19
| | | | llvm-svn: 353754
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-111-1/+1
| | | | llvm-svn: 353719
* AMDGPU/GlobalISel: Fix shift legalization for non-power-of-2Matt Arsenault2019-02-081-0/+2
| | | | | | | | clampScalar doesn't do anything for non-power-of-2 in range. There should probably be a combination rule to reduce the number of matching rules. llvm-svn: 353526
* AMDGPU/GlobalISel: Fix non-power-of-2 implicit_defMatt Arsenault2019-02-081-1/+2
| | | | llvm-svn: 353522
* AMDGPU/GlobalISel: Don't use a copy in addrspacecast loweringMatt Arsenault2019-02-081-1/+1
| | | | llvm-svn: 353516
* AMDGPU/GlobalISel: Legalize addrspacecastMatt Arsenault2019-02-081-0/+177
| | | | | | | Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
* GlobalISel: Implement narrowScalar for shift main typeMatt Arsenault2019-02-071-3/+9
| | | | | | | | | | | | | | | This is pretty much directly ported from SelectionDAG. Doesn't include the shift by non-constant but known bits version, since there isn't a globalisel version of computeKnownBits yet. This shows a disadvantage of targets not specifically which type should be used for the shift amount. If type 0 is legalized before type 1, the operations on the shift amount type use the wider type (which are also less likely to legalize). This can be avoided by targets specifying legalization actions on type 1 earlier than for type 0. llvm-svn: 353455
* AMDGPU/GlobalISel: Restrict g_implicit_def legalityMatt Arsenault2019-02-071-8/+15
| | | | llvm-svn: 353452
* AMDGPU/GlobalISel: Legalize fsqrtMatt Arsenault2019-02-071-0/+12
| | | | llvm-svn: 353438
* AMDGPU/GlobalISel: Legalize some f16 operationsMatt Arsenault2019-02-071-4/+16
| | | | llvm-svn: 353436
* GlobalISel: Implement fewerElementsVector for shiftsMatt Arsenault2019-02-071-2/+7
| | | | | | | | | Introduce a new function which handles instructions with multiple type indices, but have the same number of vector elements. Also legalize v2s16 shifts when applicable. llvm-svn: 353432
* GlobalISel: Try to make legalize rules more useful for vectorsMatt Arsenault2019-02-071-18/+7
| | | | | | | Mostly keep the existing functions on scalars, but add versions which also operate based on the vector element size. llvm-svn: 353430
* AMDGPU/GlobalISel: Legalize select for v4s16Matt Arsenault2019-02-041-3/+3
| | | | | | | Also add some more select tests to help show future legalization changes. llvm-svn: 353045
* [AMDGPU] Fix -Wunused-variable after rL352978Fangrui Song2019-02-031-1/+0
| | | | llvm-svn: 352982
* GlobalISel: Implement widenScalar for G_UNMERGE_VALUESMatt Arsenault2019-02-031-1/+2
| | | | | | | | | For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
* GlobalISel: Implement widenScalar for G_EXTRACT vector sourcesMatt Arsenault2019-02-021-0/+18
| | | | | | Handle the basic element extract case. llvm-svn: 352978
* AMDGPU/GlobalISel: Avoid reporting illegal extloads as legalMatt Arsenault2019-02-021-1/+1
| | | | | | This avoids breaking a test in a future commit. llvm-svn: 352977
* AMDGPU/GlobalISel: Legalize icmp for pointer typesMatt Arsenault2019-02-021-1/+10
| | | | llvm-svn: 352976
* AMDGPU/GlobalISel: Legalize constant for pointer typesMatt Arsenault2019-02-021-3/+4
| | | | llvm-svn: 352975
* AMDGPU/GlobalISel: Legalize select for pointer typesMatt Arsenault2019-02-021-4/+12
| | | | llvm-svn: 352974
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