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* AMDGPU: Remove llvm.AMDGPU.killMatt Arsenault2018-12-071-16/+0
| | | | | | This is the last of the old AMDGPU intrinsics. llvm-svn: 348615
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-2/+0
| | | | | | | | | | | | | | | | | | | | | Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
* AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsicTom Stellard2018-04-241-1/+0
| | | | | | | | | | | | | | Summary: This is no longer used by mesa since its 18.0.0 release. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D45988 llvm-svn: 330775
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-031-4/+0
| | | | llvm-svn: 299372
* AMDGPU: Remove llvm.AMDGPU.clamp intrinsicMatt Arsenault2017-02-211-2/+0
| | | | llvm-svn: 295789
* AMDGPU: Remove llvm.AMDGPU.flbit intrinsicMatt Arsenault2017-02-211-3/+0
| | | | llvm-svn: 295754
* AMDGPU: Remove llvm.AMDGPU.cube intrinsicMatt Arsenault2017-02-161-3/+0
| | | | llvm-svn: 295359
* AMDGPU: Remove llvm.AMDGPU.rsq intrinsicMatt Arsenault2017-02-161-5/+0
| | | | llvm-svn: 295358
* AMDGPU: Remove read_workdim intrinsicJan Vesely2016-07-251-3/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22732 llvm-svn: 276682
* AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32Matt Arsenault2016-07-181-0/+2
| | | | llvm-svn: 275871
* AMDGPU/R600: Replace barrier intrinsicsMatt Arsenault2016-07-181-4/+0
| | | | llvm-svn: 275870
* AMDGPU: Remove brev intrinsicMatt Arsenault2016-07-151-3/+0
| | | | llvm-svn: 275620
* AMDGPU: Remove legacy rsq.clamped intrinsicMatt Arsenault2016-07-151-4/+0
| | | | | | | | Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining. Also fix mismatch with non-IEEE rsq selecting to IEEE rsq. llvm-svn: 275617
* AMDGPU: Remove unused intrinsicsMatt Arsenault2016-07-141-4/+0
| | | | llvm-svn: 275371
* AMDGPU: Remove last AMDIL intrinsicsMatt Arsenault2016-07-131-6/+0
| | | | llvm-svn: 275309
* AMDGPU: Remove bfi and bfm intrinsicsMatt Arsenault2016-02-081-2/+0
| | | | | | Nothing is using them. llvm-svn: 260123
* AMDGPU: Remove 24-bit intrinsicsMatt Arsenault2016-01-291-4/+0
| | | | | | | The known bit matching code seems to work reasonably well, so these shouldn't really be needed. llvm-svn: 259180
* AMDGPU: Move AMDGPU intrinsics only used by R600Matt Arsenault2016-01-261-9/+0
| | | | llvm-svn: 258790
* AMDGPU: Add new amdgcn intrinsics for cube instructionsMatt Arsenault2016-01-261-1/+5
| | | | | | | More cleanup to try to get all intrinsics using the correct amdgcn prefix that are as close to the instruction as possible. llvm-svn: 258786
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-261-0/+9
| | | | | | Also move into backend intrinsics to discourage use of the old name. llvm-svn: 258783
* AMDGPU: Remove more unused intrinsicsMatt Arsenault2016-01-231-23/+0
| | | | | | Replace tests with lrp with basic IR expansion llvm-svn: 258612
* AMDGPU: Rename intrinsics to use amdgcn prefixMatt Arsenault2016-01-221-2/+9
| | | | | | | | | | | The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
* AMDGPU: Remove random TGSI intrinsicMatt Arsenault2016-01-221-5/+0
| | | | | | I don't think this was ever used. llvm-svn: 258514
* AMDGPU: Remove AMDGPU.fract intrinsicMatt Arsenault2016-01-221-1/+0
| | | | | | | Mesa doesn't use this, and this is pattern matched already from fsub x, (ffloor x) llvm-svn: 258513
* AMDGPU: Remove AMDGPU.trunc intrinsicMatt Arsenault2016-01-201-1/+0
| | | | llvm-svn: 258348
* AMDGPU: Remove AMDIL.fraction intrinsicMatt Arsenault2016-01-201-1/+0
| | | | llvm-svn: 258347
* AMDGPU: Remove AMDIL.round.nearest intrinsicMatt Arsenault2016-01-201-1/+0
| | | | llvm-svn: 258346
* AMDGPU: Remove abs intrinsicMatt Arsenault2016-01-201-1/+0
| | | | llvm-svn: 258343
* AMDGPU: Remove min/max intrinsicsMatt Arsenault2016-01-201-4/+0
| | | | | | This removes support for mesa 11.0.x llvm-svn: 258342
* AMDGPU: Switch barrier intrinsics to using convergentMatt Arsenault2015-12-191-2/+2
| | | | | | | | noduplicate prevents unrolling of small loops that happen to have barriers in them. If a loop has a barrier in it, it is OK to duplicate it for the unroll. llvm-svn: 256075
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+90
| | | | llvm-svn: 239657
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-64/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+64
llvm-svn: 160270
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