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* [GlobalISel] Make the InstructionSelector instance non-const, allowing state ↵Amara Emerson2019-08-131-20/+16
| | | | | | | | | | | | | | | | to be maintained. Currently we can't keep any state in the selector object that we get from subtarget. As a result we have to plumb through all our variables through multiple functions. This change makes it non-const and adds a virtual init() method to allow further state to be captured for each target. AArch64 makes use of this in this patch to cache a call to hasFnAttribute() which is expensive to call, and is used on each selection of G_BRCOND. Differential Revision: https://reviews.llvm.org/D65984 llvm-svn: 368652
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders2019-08-011-4/+4
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367633
* AMDGPU/GlobalISel: Remove manual store select codeMatt Arsenault2019-08-011-50/+2
| | | | | | | This regresses the weird types that are newly treated as legal load types, but fixes incorrectly using flat instrucions on SI. llvm-svn: 367512
* AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADDMatt Arsenault2019-08-011-0/+1
| | | | llvm-svn: 367509
* AMDGPU/GlobalISel: Allow selection of DS atomicrmwMatt Arsenault2019-08-011-4/+14
| | | | llvm-svn: 367507
* AMDGPU/GlobalISel: Select simple local storesMatt Arsenault2019-08-011-11/+18
| | | | llvm-svn: 367504
* AMDGPU/GlobalISel: Select local loadsMatt Arsenault2019-08-011-5/+79
| | | | llvm-svn: 367498
* AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting extsMatt Arsenault2019-07-241-6/+8
| | | | | | | The G_ANYEXT handling can end up reaching selectCOPY, which mutates the instruction in place. llvm-svn: 366915
* AMDGPU/GlobalISel: Remove unnecessary codeMatt Arsenault2019-07-221-4/+0
| | | | | | | The minnum/maxnum case are dead, and the cvt is handled by the default. llvm-svn: 366685
* AMDGPU/GlobalISel: Select private loadsMatt Arsenault2019-07-161-1/+135
| | | | llvm-svn: 366248
* AMDGPU/GlobalISel: Select flat storesMatt Arsenault2019-07-161-2/+4
| | | | llvm-svn: 366246
* AMDGPU/GlobalISel: Select flat loadsMatt Arsenault2019-07-161-44/+52
| | | | | | | | Now that the patterns use the new PatFrag address space support, the only blocker to importing most load patterns is the addressing mode complex patterns. llvm-svn: 366237
* AMDGPU/GlobalISel: Fix test failures in release buildMatt Arsenault2019-07-161-2/+5
| | | | | | | | | | | | Apparently the check for legal instructions during instruction select does not happen without an asserts build, so these would successfully select in release, and fail in debug. Make s16 and/or/xor legal. These can just be selected directly to the 32-bit operation, as is already done in SelectionDAG, so just make them legal. llvm-svn: 366210
* AMDGPU/GlobalISel: Select G_AND/G_OR/G_XORMatt Arsenault2019-07-151-0/+65
| | | | llvm-svn: 366121
* AMDGPU/GlobalISel: Don't constrain source register of VCC copiesMatt Arsenault2019-07-151-0/+20
| | | | | | | | | | | | | This is a hack until I come up with a better way of dealing with the pseudo-register banks used for boolean values. If the use instruction constrains the register, the selector for the def instruction won't see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have been SCCRegBank or VCCRegBank in wave32. This is necessary to successfully select branches with and and/or/xor condition. llvm-svn: 366120
* AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copiesMatt Arsenault2019-07-151-10/+12
| | | | | | | | | The extra test change is correct, although how it arrives there is a bug that needs work. With wave32, the test for isVCC ambiguously reports true for an SCC or VCC source. A new allocatable pseudo register class for SCC may be necesssary. llvm-svn: 366119
* AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCCMatt Arsenault2019-07-151-0/+4
| | | | llvm-svn: 366118
* AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCCMatt Arsenault2019-07-151-17/+23
| | | | | | This was emitting a copy from a 32-bit register to a 64-bit. llvm-svn: 366117
* AMDGPU/GlobalISel: Fix G_ICMP for wave32Matt Arsenault2019-07-151-2/+2
| | | | llvm-svn: 366114
* AMDGPU/GlobalISel: Handle llvm.amdgcn.if.breakMatt Arsenault2019-07-151-0/+25
| | | | llvm-svn: 366102
* AMDGPU/GlobalISel: Select llvm.amdgcn.end.cfMatt Arsenault2019-07-151-0/+14
| | | | llvm-svn: 366099
* AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTORMatt Arsenault2019-07-151-0/+4
| | | | llvm-svn: 366087
* AMDGPU/GlobalISel: Select G_SUBMatt Arsenault2019-07-091-6/+14
| | | | llvm-svn: 365484
* AMDGPU/GlobalISel: Select G_UNMERGE_VALUESMatt Arsenault2019-07-091-0/+46
| | | | llvm-svn: 365483
* AMDGPU/GlobalISel: Select G_MERGE_VALUESMatt Arsenault2019-07-091-0/+41
| | | | llvm-svn: 365482
* AMDGPU/GlobalISel: Try generated matcher with intrinsicsMatt Arsenault2019-07-021-8/+7
| | | | llvm-svn: 364933
* AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operandsMatt Arsenault2019-07-021-4/+6
| | | | | | | | The register bank for the destination of the sample argument copy was wrong. We shouldn't be constraining each source to the result register bank. Allow constraining the original register to the right size. llvm-svn: 364928
* AMDGPU/GlobalISel: Select G_FENCEMatt Arsenault2019-07-021-0/+5
| | | | | | | Manually select to workaround tablegen emitter emitting checks for G_CONSTANT. llvm-svn: 364927
* AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsicsMatt Arsenault2019-07-011-20/+0
| | | | llvm-svn: 364835
* AMDGPU/GlobalISel: Fail instead of assert when selecting loadsMatt Arsenault2019-07-011-5/+11
| | | | llvm-svn: 364807
* AMDGPU/GlobalISel: Complete implementation of G_GEPMatt Arsenault2019-07-011-29/+76
| | | | | | | | Also works around tablegen defect in selecting add with unused carry, but if we have to manually select GEP, might as well handle add manually. llvm-svn: 364806
* AMDGPU/GlobalISel: Select G_PHIMatt Arsenault2019-07-011-0/+40
| | | | llvm-svn: 364805
* AMDGPU/GlobalISel: Implement select for 32-bit G_ADDTom Stellard2019-07-011-2/+4
| | | | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58804 llvm-svn: 364797
* AMDGPU/GlobalISel: Select G_BRCOND for vccMatt Arsenault2019-07-011-25/+41
| | | | llvm-svn: 364795
* AMDGPU/GlobalISel: Select G_FRAME_INDEXMatt Arsenault2019-07-011-0/+18
| | | | llvm-svn: 364789
* AMDGPU/GlobalISel: Make s16 select legalMatt Arsenault2019-07-011-5/+7
| | | | | | | This is easy to handle and avoids legalization artifacts which are likely to obscure combines. llvm-svn: 364787
* AMDGPU/GlobalISel: Select G_BRCOND for scc conditionsMatt Arsenault2019-07-011-0/+33
| | | | llvm-svn: 364786
* AMDGPU/GlobalISel: Tolerate copies with no type setMatt Arsenault2019-07-011-3/+6
| | | | | | | isVCC has the same bug, but isn't used in a context where it can cause a problem. llvm-svn: 364784
* AMDGPU/GlobalISel: Select src modifiersMatt Arsenault2019-07-011-6/+40
| | | | llvm-svn: 364782
* AMDGPU/GlobalISel: Fail on store to 32-bit address spaceMatt Arsenault2019-07-011-0/+6
| | | | llvm-svn: 364766
* AMDGPU/GlobalISel: Improve icmp selection coverage.Matt Arsenault2019-07-011-13/+36
| | | | | | Select s64 eq/ne scalar icmp. llvm-svn: 364765
* AMDGPU/GlobalISel: Fix scc->vcc copy handlingMatt Arsenault2019-07-011-11/+21
| | | | | | | | | | | | | This was checking the size of the register with the value of the size, which happens to be exec. Also fix assuming VCC is 64-bit to fix wave32. Also remove some untested handling for physical registers which is skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical copy source. I'm not sure if this should be trying to handle this special case instead of dealing with this in copyPhysReg. llvm-svn: 364761
* AMDGPU/GlobalISel: Use and instead of BFE with inline immediateMatt Arsenault2019-07-011-6/+29
| | | | | | | Zext from s1 is the only case where this should do anything with the current legal extensions. llvm-svn: 364760
* AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXTMatt Arsenault2019-06-251-4/+133
| | | | llvm-svn: 364308
* AMDGPU/GlobalISel: Select G_TRUNCMatt Arsenault2019-06-241-0/+72
| | | | llvm-svn: 364215
* AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1Matt Arsenault2019-06-241-6/+11
| | | | | | Try to fail for scc, since I don't think that should ever be produced. llvm-svn: 364199
* AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic IDMatt Arsenault2019-06-171-2/+1
| | | | llvm-svn: 363578
* AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECTTom Stellard2019-06-171-0/+187
| | | | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60640 llvm-svn: 363576
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-2/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D61330 llvm-svn: 359621
* AMDGPU/GlobalISel: Implement select for G_INSERTTom Stellard2019-03-011-0/+30
| | | | | | | | | | | | Re-commit r344310. Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53116 llvm-svn: 355159
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