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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-16 18:42:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-16 18:42:53 +0000 |
| commit | dad1f89210bff2a45e23fb2a6c31ffb247450b23 (patch) | |
| tree | c11cc0dd7c0b17314cafe78de87e3928d9bb5ede /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | 11dc3d371124f329762c0f2d9a75a5a82bd00b1a (diff) | |
| download | bcm5719-llvm-dad1f89210bff2a45e23fb2a6c31ffb247450b23.tar.gz bcm5719-llvm-dad1f89210bff2a45e23fb2a6c31ffb247450b23.zip | |
AMDGPU/GlobalISel: Select flat stores
llvm-svn: 366246
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index f8f89593d08..25e72bbe75a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -856,7 +856,7 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); unsigned Opcode; - // FIXME: Select store instruction based on address space + // FIXME: Remove this when integers > s32 naturally selected. switch (StoreSize) { default: return false; @@ -1363,6 +1363,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, case TargetOpcode::G_SELECT: return selectG_SELECT(I); case TargetOpcode::G_STORE: + if (selectImpl(I, CoverageInfo)) + return true; return selectG_STORE(I); case TargetOpcode::G_TRUNC: return selectG_TRUNC(I); @@ -1545,7 +1547,7 @@ AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const { }}; } - template <bool Signed> +template <bool Signed> InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root) const { MachineInstr *MI = Root.getParent(); |

