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path: root/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
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* AMDGPU: Cleanup control flow intrinsicsMatt Arsenault2017-03-171-4/+1
| | | | | | | | | | | | | | | | Move backend internal intrinsics along with the rest of the normal intrinsics, and use the Intrinsic::getDeclaration API instead of manually constructing the type list. It's surprising this was working before. fdiv.fast had the wrong number of parameters. The control flow intrinsic declaration attributes were not being applied, and their types were inconsistent. The actual IR use types did not match the declaration, and were closer to the types used for the patterns. The brcond lowering was changing the types, so introduce new nodes for those. llvm-svn: 298119
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-5/+13
| | | | llvm-svn: 296396
* AMDGPU: Improve nsw/nuw/exact when promoting uniform i16 opsMatt Arsenault2017-02-011-18/+41
| | | | | | | | | | | | These were simply preserving the flags of the original operation, which was too conservative in most cases and incorrect for mul. nsw/nuw may be needed for some combines to cleanup messes when intermediate sext_inregs are introduced later. Tested valid combinations with alive. llvm-svn: 293776
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-201-14/+26
| | | | | | other minor fixes (NFC). llvm-svn: 292623
* AMDGPU: Allow rcp and rsq usage with f16Matt Arsenault2016-12-221-1/+0
| | | | llvm-svn: 290302
* AMDGPU: Fix crash on i16 constant expressionMatt Arsenault2016-12-061-2/+3
| | | | llvm-svn: 288861
* [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'Konstantin Zhuravlyov2016-10-071-1/+1
| | | | llvm-svn: 283558
* [AMDGPU] Promote uniform (i1, i16] operations to i32Konstantin Zhuravlyov2016-10-071-97/+101
| | | | | | Differential Revision: https://reviews.llvm.org/D25302 llvm-svn: 283555
* [AMDGPU] Promote uniform i16 bitreverse intrinsic to i32Konstantin Zhuravlyov2016-10-061-11/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D25121 llvm-svn: 283415
* [AMDGPU] Sign extend AShr when promoting (instead of zero extending)Konstantin Zhuravlyov2016-10-031-2/+2
| | | | llvm-svn: 283130
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
| | | | llvm-svn: 283004
* [AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit ↵Konstantin Zhuravlyov2016-09-281-3/+234
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D24125 llvm-svn: 282624
* AMDGPU: Use rcp for fdiv 1, x with fpmath metadataMatt Arsenault2016-07-261-1/+1
| | | | | | | Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
* AMDGPU: Change fdiv lowering based on !fpmath metadataMatt Arsenault2016-07-191-6/+117
| | | | | | | | | | | If 2.5 ulp is acceptable, denormals are not required, and isn't a reciprocal which will already be handled, replace with a faster fdiv. Simplify the lowering tests by using per function subtarget features. llvm-svn: 276051
* AMDGPU: Add stub custom CodeGenPrepare passMatt Arsenault2016-06-241-0/+82
This will do various things including ones CodeGenPrepare does, but with knowledge of uniform values. llvm-svn: 273657
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