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path: root/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
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* Use llvm::StringLiteral instead of StringRef in few placesFangrui Song2019-09-201-12/+6
| | | | llvm-svn: 372395
* AMDGPU: Add intrinsics for address space identificationMatt Arsenault2019-09-051-0/+3
| | | | | | | The library currently uses ptrtoint and directly checks the queue ptr for this, which counts as a pointer capture. llvm-svn: 371009
* AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV)Aakanksha Patil2019-03-071-5/+63
| | | | | | | | | | A previous patch for "uniform-work-group-size" attribute was found to break some RADV and possibly radeon SI tests and had to be retracted. This patch fixes that. Differential Revision: http://reviews.llvm.org/D58993 llvm-svn: 355574
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-131-62/+6
| | | | | | This patch breaks RADV (and probably RadeonSI as well) llvm-svn: 349084
* [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-121-6/+62
| | | | | | | | Updated the annotate-kernel-features pass to support the propagation of uniform-work-group attribute from the kernel to the called functions. Once this pass is run, all kernels, even the ones which initially did not have the attribute, will be able to indicate weather or not they have uniform work group size depending on the value of the attribute. Differential Revision: https://reviews.llvm.org/D50200 llvm-svn: 348971
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-18/+12
| | | | llvm-svn: 341165
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-1/+1
| | | | | | | | | | | | | | | | | Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
* [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-311-4/+19
| | | | | | warnings; other minor fixes. Also affected in files (NFC). llvm-svn: 312289
* AMDGPU: Annotate implicitarg.ptr usageMatt Arsenault2017-07-281-2/+4
| | | | | | | | | | | We need to pass something to functions for this to work. It isn't derivable just from the kernarg segment pointer because the implicit arguments are placed after the kernel arguments. Also fixes missing test for the intrinsic. llvm-svn: 309398
* AMDGPU: Annotate necessity of flat-scratch-initMatt Arsenault2017-07-181-2/+17
| | | | | | | | As an approximation of the existing handling to avoid regressions. Fixes using too many registers with calls on subtargets with the SGPR allocation bug. llvm-svn: 308326
* AMDGPU: Annotate features from x work item/group IDs.Matt Arsenault2017-07-171-6/+17
| | | | | | | | This wasn't necessary before since they are always enabled for kernels, but this is necessary if they need to be forwarded to a callable function. llvm-svn: 308226
* [AMDGPU] Throw away more dead code. NFCI.Davide Italiano2017-07-141-16/+0
| | | | llvm-svn: 308055
* [AMDGPU] Garbage collect dead code. NFCI.Davide Italiano2017-07-141-16/+0
| | | | | | Unbreaks the build with GCC7. llvm-svn: 308047
* AMDGPU: Detect kernarg segment pointerMatt Arsenault2017-07-141-1/+5
| | | | | | | | This is necessary to pass the kernarg segment pointer to callee functions. Also don't unconditionally enable for kernels. llvm-svn: 307978
* AMDGPU: Annotate call graph with used featuresMatt Arsenault2017-07-131-67/+143
| | | | | | | Previously this wouldn't detect used features indirectly used in callee functions. llvm-svn: 307967
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-15/+22
| | | | | | | | | | | | | | | | | | As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-4/+9
| | | | llvm-svn: 295554
* AMDGPU : Add trap handler support.Wei Ding2017-02-101-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D26010 llvm-svn: 294692
* AMDGPU : Add trap handler support.Wei Ding2017-01-241-1/+2
| | | | llvm-svn: 292893
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-161-1/+1
| | | | | | | | | | | | | | Summary: mesa3d will use the same kernel calling convention as amdhsa, but it will handle everything else like the default 'unknown' OS type. Reviewers: arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22783 llvm-svn: 281779
* AMDGPU: Prune includesMatt Arsenault2016-08-111-0/+1
| | | | llvm-svn: 278391
* AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault2016-07-221-1/+2
| | | | llvm-svn: 276437
* AMDGPU: Fix constantexpr addrspacecastsMatt Arsenault2016-06-061-3/+67
| | | | | | | | If we had a constant group address space cast the queue pointer wasn't enabled for the function, resulting in a crash on noreg later. llvm-svn: 271935
* AMDGPU: Implement addrspacecastMatt Arsenault2016-04-251-5/+33
| | | | llvm-svn: 267452
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-251-1/+2
| | | | llvm-svn: 267451
* AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptrMatt Arsenault2016-01-301-9/+4
| | | | | | | | Only the dispatch.ptr intrinsic is supposed to be used now to get the workgroup size, and the read.local.size intrinsics do not work correctly. llvm-svn: 259296
* AMDGPU: Add new amdgcn workitem intrinsicsMatt Arsenault2016-01-301-0/+6
| | | | | | | These use the correct prefix and follow the HSA naming convention rather than the config register option names. llvm-svn: 259293
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-261-1/+2
| | | | | | | | | | | | | | Summary: This returns a pointer to the dispatch packet, which can be used to load information about the kernel dispach. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D14898 llvm-svn: 254116
* AMDGPU: Add pass to detect used kernel featuresMatt Arsenault2015-11-061-0/+125
Mark kernels that use certain features that require user SGPRs to support with kernel attributes. We need to know before instruction selection begins because it impacts the kernel calling convention lowering. For now this only detects the workitem intrinsics. llvm-svn: 252323
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