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* [AArch64] Cleanup sign extend in genAlternativeCodeSequenceDavid Majnemer2016-07-211-3/+3
| | | | | | | | Use the machinery in MathExtras instead of rolling it by hand. This fixes PR28624. llvm-svn: 276366
* [AArch64][Inline-Asm] Return the 32-bit floating point register classAkira Hatanaka2016-07-211-1/+1
| | | | | | | | | | | | | | | when constraint "w" is used on a 32-bit operand. This enables compiling the following code, which used to error out in the backend: void foo1(int a) { asm volatile ("sqxtn h0, %s0\n" : : "w"(a):); } Fixes PR28633. llvm-svn: 276344
* [AArch64] Load/store opt: Don't count transient instructions towards search ↵Geoff Berry2016-07-211-15/+14
| | | | | | | | | | | | | | | | | | limits. Summary: This change also changes findMatchingInsn and findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account when tracking register defs and uses, which could potentially inhibit these optimizations in the presence of debug information. Reviewers: mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22582 llvm-svn: 276293
* [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc ↵Geoff Berry2016-07-204-8/+2
| | | | | | -run-pass. NFCI. llvm-svn: 276193
* [AArch64][FastISel] Select -O0 legal cmpxchg.Ahmed Bougacha2016-07-201-0/+55
| | | | | | | | | | | At -O0, cmpxchg survives AtomicExpand: it's mostly straightforward to select it in fast-isel, and let the pseudo be expanded later. extractvalues on the result are the tricky part: the generic logic only works for legal types (and it would be painful to make it support illegal types), so we can only support i32/i64 cmpxchg. llvm-svn: 276183
* [AArch64][FastISel] Select atomic stores into STLR.Ahmed Bougacha2016-07-201-3/+40
| | | | llvm-svn: 276182
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-202-0/+27
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* Revert "Disable this-return argument forwarding on ARM/AArch64"David Majnemer2016-07-201-8/+1
| | | | | | | | | Inference of the 'returned' attribute was fixed in r276008, lets try turning the backend support back on. This reverts commit r275677. llvm-svn: 276081
* [AArch64] Properly validate the reciprocal estimation.Evandro Menezes2016-07-191-0/+6
| | | | | | | | Add check for legal data types when expanding into a Newton series. Differential Revision: https://reviews.llvm.org/D22267 llvm-svn: 276041
* [AArch64] PredictableSelectIsExpensive for Vulcan.Pankaj Gode2016-07-191-0/+1
| | | | | | | | Adding PredictableSelectIsExpensive for Vulcan Differential Revision: https://reviews.llvm.org/D22448 llvm-svn: 275978
* Disable this-return argument forwarding on ARM/AArch64Hal Finkel2016-07-161-1/+8
| | | | | | | | | | | r275042 reverted function-attribute inference for the 'returned' attribute because the feature triggered self-hosting failures on ARM and AArch64. James Molloy determined that the this-return argument forwarding feature, which directly ties the returned input argument to the returned value, was the cause. It seems likely that this forwarding code contains, or triggers, a subtle bug. Disabling for now until we can track that down. llvm-svn: 275677
* Minor code cleanups. NFC.Junmo Park2016-07-151-2/+2
| | | | llvm-svn: 275637
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-40/+35
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-151-3/+3
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-156-13/+13
| | | | | | | | | | | | Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
* [AArch64] Set COPY ZR isAsCheapAsAMove when needed.Haicheng Wu2016-07-151-2/+6
| | | | | | | | | If a subtarget has both ZCZeroing and CustomCheapAsMoveHandling features (now only Kryo has both), set COPY (W|X)ZR isAsCheapAsAMove. Differential Revision: http://reviews.llvm.org/D22360 llvm-svn: 275503
* s/constexpr/LLVM_CONSTEXPR in AArch64InstrInfo.cpp.Justin Lebar2016-07-141-1/+1
| | | | | | Yet again. llvm-svn: 275463
* [AArch64] Adjust the scheduling model for Exynos-M1.Evandro Menezes2016-07-141-0/+1
| | | | | | Enable use-postra-scheduler. (NFC) llvm-svn: 275457
* [CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.Justin Lebar2016-07-142-21/+7
| | | | | | | | | | | | | | | | | Summary: Make the target-specific flags in MachineMemOperand::Flags real, bona fide enum values. This simplifies users, prevents various constants from going out of sync, and avoids the false sense of security provided by declaring static members in classes and then forgetting to define them inside of cpp files. Reviewers: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22372 llvm-svn: 275451
* [CodeGen] Refactor MachineMemOperand's Flags enum.Justin Lebar2016-07-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: - Give it a shorter name (because we're going to refer to it often from SelectionDAG and friends). - Split the flags and alignment into separate variables. - Specialize FlagsEnumTraits for it, so we can do bitwise ops on it without losing type information. - Make some enum values constants in MachineMemOperand instead. MOMaxBits should not be a valid Flag. - Simplify some of the bitwise ops for dealing with Flags. Reviewers: chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22281 llvm-svn: 275438
* [AArch64] Set FMOVS0 and FMOVD0 as isAsCheapAsAMove when needed.Haicheng Wu2016-07-121-0/+6
| | | | | | | | | If a subtarget has both ZCZeroing and CustomCheapAsMoveHandling features (now only Kryo has both), set FMOVS0 and FMOVD0 isAsCheapAsAMove. Differential Revision: http://reviews.llvm.org/D22256 llvm-svn: 275178
* [Kryo] Enable ZCZeroing featureHaicheng Wu2016-07-121-1/+2
| | | | | | | | This feature uses immediate #0 to zero a register. Differential Revision: http://reviews.llvm.org/D19985 llvm-svn: 275143
* Fix branch relaxation in 16-bit mode.Nirav Dave2016-07-111-1/+3
| | | | | | | | | | | | | | | Thread through MCSubtargetInfo to relaxInstruction function allowing relaxation to generate jumps with 16-bit sized immediates in 16-bit mode. This fixes PR22097. Reviewers: dwmw2, tstellarAMD, craig.topper, jyknight Subscribers: jfb, arsenm, jyknight, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D20830 llvm-svn: 275068
* AArch64: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-088-222/+217
| | | | | | | | Avoid implicit conversions from MachineInstrBundleInstr to MachineInstr* in the AArch64 backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable. llvm-svn: 274924
* Target: Avoid getFirstTerminator() => pointer, NFCDuncan P. N. Exon Smith2016-07-082-9/+9
| | | | | | | | | | | | | | Stop using an implicit conversion from the return of MachineBasicBlock::getFirstTerminator to MachineInstr*. In two cases, directly dereference to a MachineInstr& since later code assumes it's valid. In a third case, change to an iterator since later code checks against MachineBasicBlock::end. Although the fix for the third case avoids undefined behaviour, I expect this doesn't cause a functionality change in practice (since the basic block already has a terminator). llvm-svn: 274898
* [AArch64] Macro fusion of simple ALU ops with branches for Broadcom's VulcanPankaj Gode2016-07-081-0/+1
| | | | | | | | | | Support for the macro fusion of simple ALU ops with branches for the Vulcan sub-target. Patch by Meador Inge <meadori@gmail.com> Differential Revision: http://reviews.llvm.org/D22042 llvm-svn: 274837
* [AArch64] Change the preferred alignment for char and short to word alignment.Chad Rosier2016-07-071-2/+2
| | | | | | | | | | The commit reinstates r273279, which was informally approved. Original Review: http://reviews.llvm.org/D21414 This reverts commit ca632c91aaa7cafc50942f890c49f727a046ace1. llvm-svn: 274790
* Revert "[AArch64] Change the preferred alignment for char and short to word ↵Chad Rosier2016-07-071-2/+2
| | | | | | | | alignment" This reverts commit r273279 as the change was not properly approved. llvm-svn: 274768
* fix documentation comment. NFC.Junmo Park2016-07-061-2/+1
| | | | llvm-svn: 274704
* Minor code cleanup. NFC.Junmo Park2016-07-061-1/+1
| | | | llvm-svn: 274702
* AArch64: Change modeling of zero cycle zeroing.Matthias Braun2016-07-062-24/+48
| | | | | | | | | | | | | | | | | On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should be used to zero a vector register. This was previously done at instruction selection time, however the register coalescer sometimes widened multiple vregs to the Q width because of that leading to extra spills. This patch leaves the decision on how to zero a register to the AsmPrinter phase where it doesn't affect register allocation anymore. This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0. This fixes http://llvm.org/PR27454, rdar://25866262 Differential Revision: http://reviews.llvm.org/D21826 llvm-svn: 274686
* AArch64: Replace a RegScavenger instance with LivePhysRegsMatthias Braun2016-07-061-14/+14
| | | | | | | | | | | | | | findScratchNonCalleeSaveRegister() just needs a simple liveness analysis, use LivePhysRegs for that as it is simpler and does not depend on the kill flags. This commit adds a convenience function available() to LivePhysRegs: This function returns true if the given register is not reserved and neither the register nor any of its aliases are alive. Differential Revision: http://reviews.llvm.org/D21865 llvm-svn: 274685
* AArch64: try to fix optimized build failure.Tim Northover2016-07-051-1/+2
| | | | | | | | | I think the Ops filled out by Regex::match contain pointers into the temporary std::string returned by StringRef::upper. Its lifetime is extended by the call to match, but only until the end of that call (not to the uses of Ops later on). llvm-svn: 274586
* Fix an ordering problem in r274431Manman Ren2016-07-051-1/+1
| | | | llvm-svn: 274582
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-0510-1959/+1255
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* Revert r259387: "AArch64: Implement missed conditional compare sequences."Balaram Makam2016-07-052-47/+2
| | | | | | | This reverts commit r259387 because it inserts illegal code after legalization in some backends where i64 OR type is illegal for example. llvm-svn: 274573
* AArch64: use correct SDValue # when looking for bitfield placement.Tim Northover2016-07-051-2/+3
| | | | | | | | | | The other use really does only care about the SDNode (it checks the opcode against a whitelist), but bitFieldPlacement can be misled if the node produces multiple results. Patch by Ismail Badawi. llvm-svn: 274567
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-023-23/+14
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-011-2/+2
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-012-4/+2
| | | | | | | | | | TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-302-15/+14
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* Delete MCCodeGenInfo.Rafael Espindola2016-06-301-10/+3
| | | | | | | MC doesn't really care about CodeGen stuff, so this was just complicating target initialization. llvm-svn: 274258
* Delete unused includes. NFC.Rafael Espindola2016-06-301-1/+0
| | | | llvm-svn: 274225
* [AArch64] Add Broadcom Vulcan scheduling model.Pankaj Gode2016-06-303-4/+863
| | | | | | | | Adding scheduling model for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21728 llvm-svn: 274213
* Use ShuffleVectorSDNode::isSplat member method instead of static method ↵Craig Topper2016-06-301-2/+1
| | | | | | isSplatMask where the mask came directly from getMask() on a shuffle node. llvm-svn: 274208
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-307-247/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* AArch64: Remove unnecessary namespace llvm; NFCMatthias Braun2016-06-281-4/+0
| | | | llvm-svn: 273975
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-271-2/+1
| | | | | | Should fix the shared library build. llvm-svn: 273958
* [AArch64] Adjust the model for the vector by element FP multiplies on Exynos ↵Evandro Menezes2016-06-241-4/+4
| | | | | | M1. (NFC) llvm-svn: 273708
* [AArch64] Model the cost of vector by element FP multiplies on Exynos M1. (NFC)Evandro Menezes2016-06-231-0/+6
| | | | llvm-svn: 273630
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