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* [AArch64] Missing aliases for CMP/CMN [W]SP with no shiftArtyom Skrobov2014-06-091-0/+4
| | | | llvm-svn: 210464
* [AArch64] Fix the ordering of the accumulate operand in SchedRW list.Chad Rosier2014-06-091-3/+3
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 llvm-svn: 210446
* [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shiftChad Rosier2014-06-091-9/+9
| | | | | | | plus add. The shift can be folded into the add. This only effects codegen when the constant is 3. llvm-svn: 210445
* [C++11] Use 'nullptr'.Craig Topper2014-06-081-1/+1
| | | | llvm-svn: 210442
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-135/+122
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* Remove outdated CMake MSVC workaroundAlp Toker2014-06-081-7/+1
| | | | llvm-svn: 210421
* Have TargetSelectionDAGInfo take a DataLayout initializer rather thanEric Christopher2014-06-061-1/+1
| | | | | | a TargetMachine since the only thing it wants is DataLayout. llvm-svn: 210366
* [AArch64] clang-format the load/store optimizer.Tilmann Scheller2014-06-041-16/+25
| | | | | | No change in functionality. llvm-svn: 210182
* [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.Tilmann Scheller2014-06-041-19/+19
| | | | | | | | Variable names should start with an upper case letter. No change in functionality. llvm-svn: 210181
* [AArch64] Fix typo in load/store optimizer.Tilmann Scheller2014-06-031-1/+1
| | | | llvm-svn: 210114
* AArch64: mark small types (i1, i8, i16) as promotedTim Northover2014-06-033-21/+13
| | | | | | | | | This means the output of LowerFormalArguments returns a lowered SDValue with the correct type (expected in SelectionDAGBuilder). Without this, an assertion under a DEBUG macro triggers when those types are passed on the stack. llvm-svn: 210102
* [AArch64] Correctly deal with VPR stack parameter passing.Jiangning Liu2014-06-031-3/+10
| | | | llvm-svn: 210067
* Fix typosAlp Toker2014-05-311-2/+2
| | | | llvm-svn: 209982
* Have the TLOF creation take a Triple rather than needing a subtarget.Eric Christopher2014-05-311-3/+3
| | | | llvm-svn: 209937
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-301-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
* Restore getInvertedCondCode() from the phased-out backend, fixing ↵Artyom Skrobov2014-05-291-17/+3
| | | | | | disassembly for NV llvm-svn: 209803
* Add missing check when MatchInstructionImpl() reports failureArtyom Skrobov2014-05-291-0/+2
| | | | llvm-svn: 209802
* Fix an assertion failure caused by v1i64 in DAGCombiner Shrink.Hao Liu2014-05-291-16/+9
| | | | llvm-svn: 209798
* [pr19844] Add thread local mode to aliases.Rafael Espindola2014-05-281-9/+3
| | | | | | | | | | This matches gcc's behavior. It also seems natural given that aliases contain other properties that govern how it is accessed (linkage, visibility, dll storage). Clang still has to be updated to expose this feature to C. llvm-svn: 209759
* AArch64: implement copies to/from NZCV as a last ditch effort.Tim Northover2014-05-272-2/+20
| | | | | | | | | | A test in test/Generic creates a DAG where the NZCV output of an ADCS is used by multiple nodes. This makes LLVM want to save a copy of NZCV for later, which it couldn't do before. This should be the last fix required for the aarch64 buildbot. llvm-svn: 209651
* AArch64: support 'c' and 'n' inline asm modifiers.Tim Northover2014-05-271-0/+5
| | | | | | | These are tested by test/CodeGen/Generic, so we should probably know how to deal with them. Fortunately generic code does it if asked. llvm-svn: 209646
* AArch64: force i1 to be zero-extended at an ABI boundary.Tim Northover2014-05-261-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is debatable. There are two possible approaches, neither of which is really satisfactory: 1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin, and 8 bits otherwise. 2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller to 8 bits. This goes against the spirit of "zeroext" I think, but it's a bit of a vague construct anyway (by definition you're going to extend to the amount required by the ABI, that's why it's the ABI!). This implements option 2. The DAG machinery really isn't setup for the first (there's a fairly strong assumption that "zeroext" goes to at least the smallest register size), and even if it was the resulting DAG looks like it would be inferior in many cases. Theoretically we could add AssertZext nodes in the consumers of ABI-passed values too now, but this actually seems to make the code worse in practice by making truncation proceed in two steps. The code produced is equally valid if we continue to assume only the low bit is defined. Should fix PR19850 llvm-svn: 209637
* AArch64: simplify calling conventions slightly.Tim Northover2014-05-264-128/+36
| | | | | | | | | We can eliminate the custom C++ code in favour of some TableGen to check the same things. Functionality should be identical, except for a buffer overrun that was present in the C++ code and meant webkit failed if any small argument needed to be passed on the stack. llvm-svn: 209636
* AArch64: disable FastISel for large code model.Tim Northover2014-05-241-0/+5
| | | | | | | | | The code emitted is what would be expected for the small model, so it shouldn't be used when objects can be the full 64-bits away. This fixes MCJIT tests on Linux. llvm-svn: 209585
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-2491-0/+62229
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-2474-38972/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-191-0/+2
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-171-5/+5
| | | | | | | | | | This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-162-18/+0
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* AArch64: disable printing of add/sub aliasTim Northover2014-05-161-1/+2
| | | | | | | | | | This alias appears not to have an appropriate PrintMethod. Normally, I'd look into it, but since AArch64 is disappearing soon it's probably not worth it. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208967
* AArch64: disable printing of MOV -> MOVZ aliasesTim Northover2014-05-161-1/+1
| | | | | | | | | | Actually, MOV sometimes is canonical, but for now this is a better approximation than what's there. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208962
* Implement global merge optimization for global variables.Jiangning Liu2014-05-152-0/+18
| | | | | | | | | | | This commit implements two command line switches -global-merge-on-external and -global-merge-aligned, and both of them are false by default, so this optimization is disabled by default for all targets. For ARM64, some back-end behaviors need to be tuned to get this optimization further enabled. llvm-svn: 208934
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-4/+2
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-123-3/+17
| | | | llvm-svn: 208607
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-112-2/+3
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-111-1/+1
| | | | | | No functionality change intended. llvm-svn: 208507
* Implememting named register intrinsicsRenato Golin2014-05-062-0/+14
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* AArch64: Mark vector long multiplication as expand.Benjamin Kramer2014-04-291-0/+5
| | | | | | | There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. llvm-svn: 207515
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2922-130/+137
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [C++] Use 'nullptr'.Craig Topper2014-04-282-3/+3
| | | | llvm-svn: 207394
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+1
| | | | llvm-svn: 207377
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-2/+2
| | | | llvm-svn: 207374
* Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer ↵Craig Topper2014-04-261-3/+2
| | | | | | and size. llvm-svn: 207329
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-15/+9
| | | | llvm-svn: 207327
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-258-23/+23
| | | | llvm-svn: 207197
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-241-0/+4
| | | | | | | | | | | | This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 llvm-svn: 207143
* AArch64: print NEON lists with a space.Tim Northover2014-04-241-2/+2
| | | | | | | This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. llvm-svn: 207116
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 llvm-svn: 206906
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-223-0/+20
| | | | llvm-svn: 206861
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