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* Add subtarget caches to aarch64, arm, ppc, and x86.Eric Christopher2014-10-062-1/+31
| | | | | | | | | These will make it easier to test further changes to the code generation and optimization pipelines as those are moved to subtargets initialized with target feature and target cpu. llvm-svn: 219106
* Make AAMDNodes ctor and operator bool (!!!) explicit, mop up bugs and ↵Benjamin Kramer2014-10-041-1/+1
| | | | | | weirdness exposed by it. llvm-svn: 219068
* Add fake use to suppress defined-but-unused warningsJingyue Wu2014-10-041-0/+1
| | | | llvm-svn: 219045
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-031-2/+2
| | | | llvm-svn: 218999
* constify TargetMachine parameter.Eric Christopher2014-10-034-5/+6
| | | | llvm-svn: 218934
* [Stackmaps] Make ithe frame-pointer required for stackmaps.Juergen Ributzka2014-10-021-1/+2
| | | | | | | | | Do not eliminate the frame pointer if there is a stackmap or patchpoint in the function. All stackmap references should be FP relative. This fixes PR21107. llvm-svn: 218920
* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-012-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! Note: I accidentally committed a bogus older version of this patch previously. llvm-svn: 218787
* Revert r218778 while investigating buldbot breakage.Adrian Prantl2014-10-012-7/+8
| | | | | | "Move the complex address expression out of DIVariable and into an extra" llvm-svn: 218782
* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-012-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! llvm-svn: 218778
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-015-60/+26
| | | | | | | | | | | | | | | | | | | | | The A64 instruction set includes a generic register syntax for accessing implementation-defined system registers. The syntax for these registers is: S<op0>_<op1>_<CRn>_<CRm>_<op2> The encoding space permitted for implementation-defined system registers is: op0 op1 CRn CRm op2 11 xxx 1x11 xxxx xxx The full encoding space can now be accessed: op0 op1 CRn CRm op2 xx xxx xxxx xxxx xxx This is useful to anyone needing to write assembly code supporting new system registers before the assembler has learned the official names for them. llvm-svn: 218753
* Add missing natual vector cast.Asiri Rathnayake2014-10-012-0/+2
| | | | | | | | | Summary: The natual vector cast node (similar to bitcast) AArch64ISD::NVCAST was introduced in r217159 and r217138. This patch adds a missing cast from v2f32 to v1i64 which is causing some compilation failures. Also added test cases to cover various modimm types and BUILD_VECTORs with i64 elements. llvm-svn: 218751
* Recommit r218010 [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.Juergen Ributzka2014-09-301-54/+116
| | | | | | | | | | | | | | Note: This version fixed an issue with the TBZ/TBNZ instructions that were generated in FastISel. The issue was that the 64bit version of TBZ (TBZX) automagically sets the upper bit of the immediate field that is used to specify the bit we want to test. To test for any of the lower 32bits we have to first extract the subregister and use the 32bit version of the TBZ instruction (TBZW). Original commit message: Teach selectBranch to fold bit test and branch into a single instruction (TBZ or TBNZ). llvm-svn: 218693
* [AArch64] Remove unnecessary whitespace. (Test commit)Tom Coxon2014-09-301-2/+2
| | | | llvm-svn: 218680
* [FastISel][AArch64] Fold sign-/zero-extends into the load instruction.Juergen Ributzka2014-09-301-135/+220
| | | | | | | | | | | | | | The sign-/zero-extension of the loaded value can be performed by the memory instruction for free. If the result of the load has only one use and the use is a sign-/zero-extend, then we emit the proper load instruction. The extend is only a register copy and will be optimized away later on. Other instructions that consume the sign-/zero-extended value are also made aware of this fact, so they don't fold the extend too. This fixes rdar://problem/18495928. llvm-svn: 218653
* [FastISel][AArch64] Factor out scale factor calculation. NFC.Juergen Ributzka2014-09-301-35/+29
| | | | | | | Factor out the code that determines the implicit scale factor of memory operations for a given value type. llvm-svn: 218652
* [AArch64] Refines the Cortex-A57 Machine ModelDave Estes2014-09-292-24/+395
| | | | | | | | | | | | | | | Primarily refines all of the instructions with accurate latency and micro-op information. Refinements largely focus on the NEON instructions. Additionally, a few advanced features are modeled, including forwarding for MAC instructions and hazards for floating point SQRT and DIV. Lastly, the issue-width is reduced to three so that the scheduler will better accommodate the narrower decode and dispatch width. llvm-svn: 218627
* [AArch64] Improve cost model to handle sdiv by a pow-of-two.Chad Rosier2014-09-291-0/+23
| | | | | | | | | | | This patch improves the target-specific cost model to better handle signed division by a power of two. The immediate result is that this enables the SLP vectorizer to do a better job. http://reviews.llvm.org/D5469 PR20714 llvm-svn: 218607
* AArch64: allow constant expressions for shifted reg literalsJim Grosbach2014-09-231-6/+7
| | | | | | | | | | | | e.g., add w1, w2, w3, lsl #(2 - 1) This sort of thing comes up in pre-processed assembly playing macro games. Still validate that it's an assembly time constant. The early exit error check was just a bit overzealous and disallowed a left paren. rdar://18430542 llvm-svn: 218336
* Fix segfault in AArch64 backend with -g and -mbig-endianOliver Stannard2014-09-231-2/+2
| | | | | | | Fix a null pointer dereference when trying to swap the endianness of fixups in the .eh_frame section in the AArch64 backend. llvm-svn: 218311
* [FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left ↵Juergen Ributzka2014-09-221-2/+3
| | | | | | | | | | | for booleans (i1). Shift-left immediate with sign-/zero-extensions also works for boolean values. Update the assert and the test cases to reflect that fact. This should fix a bug found by Chad. llvm-svn: 218275
* [FastIsel][AArch64] Fix a think-o in address computation.Juergen Ributzka2014-09-191-20/+27
| | | | | | | | | | When looking through sign/zero-extensions the code would always assume there is such an extension instruction and use the wrong operand for the address. There was also a minor issue in the handling of 'AND' instructions. I accidentially used a 'cast' instead of a 'dyn_cast'. llvm-svn: 218161
* Reverting NFC changes from r218050. Instead, the warning was disabled for ↵Aaron Ballman2014-09-181-1/+0
| | | | | | GCC in r218059, so these changes are no longer required. llvm-svn: 218062
* Fixing a bunch of -Woverloaded-virtual warnings due to hiding ↵Aaron Ballman2014-09-181-0/+1
| | | | | | getSubtargetImpl from the base class. NFC. llvm-svn: 218050
* Revert "[FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ."Juergen Ributzka2014-09-181-32/+8
| | | | | | Reverting it until I have time to investigate a regression. llvm-svn: 218035
* Fix previous commit: [FastISel][AArch64] Simplify XALU multiplies.Juergen Ributzka2014-09-181-8/+42
| | | | | | | | When folding the intrinsic flag into the branch or select we also have to consider the fact if the intrinsic got simplified, because it changes the flag we have to check for. llvm-svn: 218034
* [FastISel][AArch64] Simplify XALU multiplies.Juergen Ributzka2014-09-181-1/+22
| | | | | | Simplify {s|u}mul.with.overflow to {s|u}add.with.overflow when possible. llvm-svn: 218033
* [FastISel][AArch64] Followup commit for 218031 to handle negative offsets too.Juergen Ributzka2014-09-181-3/+7
| | | | llvm-svn: 218032
* [FastISel][AArch64] Try to fold the offset into the add instruction when ↵Juergen Ributzka2014-09-181-4/+10
| | | | | | | | | | | | simplifying a memory address. Small optimization in 'simplifyAddress'. When the offset cannot be encoded in the load/store instruction, then we need to materialize the address manually. The add instruction can encode a wider range of immediates than the load/store instructions. This change tries to fold the offset into the add instruction first before materializing the offset in a register. llvm-svn: 218031
* [FastISel][AArch64] Fold 'AND' instruction during the address computation.Juergen Ributzka2014-09-181-0/+54
| | | | | | | | | | | The 'AND' instruction could be used to mask out the lower 32 bits of a register. If this is done inside an address computation we might be able to fold the instruction into the memory instruction itself. and x1, x1, #0xffffffff ---> ldrb x0, [x0, w1, uxtw] ldrb x0, [x0, x1] llvm-svn: 218030
* [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.Juergen Ributzka2014-09-181-8/+32
| | | | | | | Teach selectBranch to fold bit test and branch into a single instruction (TBZ or TBNZ). llvm-svn: 218010
* [FastISel][AArch64] Custom lower sdiv by power-of-2.Juergen Ributzka2014-09-171-0/+72
| | | | | | | | | Emit an optimized instruction sequence for sdiv by power-of-2 depending on the exact flag. This fixes rdar://problem/18224511. llvm-svn: 217986
* [FastISel][AArch64] Simplify mul to shift when possible.Juergen Ributzka2014-09-171-12/+48
| | | | | | This is related to rdar://problem/18369687. llvm-svn: 217980
* [FastISel][AArch64] Fold mul into add/sub and logical operations.Juergen Ributzka2014-09-171-19/+69
| | | | | | | | | Try to fold the multiply into the add/sub or logical operations (when possible). This is related to rdar://problem/18369687. llvm-svn: 217978
* [FastISel][AArch64] Fold mul into the address computation of memory operations.Juergen Ributzka2014-09-171-0/+70
| | | | | | | | | Teach 'computeAddress' to also fold multiplies into the address computation (when possible). This fixes rdar://problem/18369443. llvm-svn: 217977
* [FastISel][AArch64] Fold compare with zero and branch into CBZ and CBNZ.Juergen Ributzka2014-09-171-0/+64
| | | | | | | | | This takes advanatage of the CBZ and CBNZ instruction to further optimize the common null check pattern into a single instruction. This is related to rdar://problem/18358882. llvm-svn: 217972
* [FastISel][AArch64] Improve branch selection to support all FP conditions.Juergen Ributzka2014-09-171-10/+48
| | | | | | | | | | | | This adds the last two missing floating-point condition codes (FCMP_UEQ and FCMP_ONE) also to the branch selection. In these two cases an additonal branch instruction is required. This also adds unit tests to checks all the different condition codes. This is related o rdar://problem/18358882. llvm-svn: 217966
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-172-0/+5
| | | | | | | | | | | | This required a new hook called hasLoadLinkedStoreConditional to know whether to expand atomics to LL/SC (ARM, AArch64, in a future patch Power) or to CmpXchg (X86). Apart from that, the new code in AtomicExpandPass is mostly moved from X86AtomicExpandPass. The main result of this patch is to get rid of that pass, which had lots of code duplicated with AtomicExpandPass. llvm-svn: 217928
* [FastISel][AArch64] Add vector support to argument lowering.Juergen Ributzka2014-09-161-42/+44
| | | | | | Lower the first 8 vector arguments too. llvm-svn: 217850
* [FastISel][AArch64] Allow handling of vectors during return lowering for ↵Juergen Ributzka2014-09-151-2/+7
| | | | | | | | | | little endian machines. Allow handling of vectors during return lowering at least for little endian machines. This was restricted in r208200 to fix it for big endian machines (according to the comment), but it also disabled it for little endian too. llvm-svn: 217846
* [FastISel][AArch64] Update function and variable names to follow the coding ↵Juergen Ributzka2014-09-151-164/+162
| | | | | | standard. NFC. llvm-svn: 217845
* [FastISel][AArch64] Make AArch64FastISel class final. NFC.Juergen Ributzka2014-09-151-1/+1
| | | | llvm-svn: 217840
* [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.Juergen Ributzka2014-09-151-0/+50
| | | | | | | | Also lower sin/cos/pow to runtime lib calls. This fixes rdar://problem/18343468. llvm-svn: 217839
* [FastISel][AArch64] Add lowering support for frem.Juergen Ributzka2014-09-151-1/+44
| | | | | | | | | | | This lowers frem to a runtime libcall inside fast-isel. The test case also checks the CallLoweringInfo bug that was exposed by this change. This fixes rdar://problem/18342783. llvm-svn: 217833
* [FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. ↵Juergen Ributzka2014-09-151-27/+41
| | | | | | | | NFC. Small refactor to tidy up the code a little. llvm-svn: 217827
* [FastISel][AArch64] Refactor code to use isTypeSupported. NFC.Juergen Ributzka2014-09-151-19/+6
| | | | | | Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported. llvm-svn: 217826
* [FastISel][AArch64] Improve floating-point compare support.Juergen Ributzka2014-09-151-7/+62
| | | | | | | | Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. llvm-svn: 217823
* [A57FPLoadBalancing] Modify r217689 - actually we do need to check defsJames Molloy2014-09-141-6/+6
| | | | | | | | ... Just make sure we check uses first so we see the kill first. It turns out ignoring defs gives some pretty nasty runtime failures. I'm certain this is the fix but I'm still reducing a testcase. llvm-svn: 217735
* [FastISel][AArch64] Add support for non-native types for logical ops.Juergen Ributzka2014-09-131-36/+48
| | | | | | | | | Extend the logical ops selection to also support non-native types such as i1, i8, and i16. Fixes rdar://problem/18330589. llvm-svn: 217732
* [AArch64] Don't enable the post-RA MI scheduler at OptNone.Chad Rosier2014-09-121-1/+2
| | | | | | Hopefully, this will appease the bots. llvm-svn: 217712
* [AArch64] Enable post-RA MI scheduler.Chad Rosier2014-09-122-1/+6
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5278 Patch by Sanjin Sijaric! llvm-svn: 217693
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