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* Distinguish between code pointer size and DataLayout::getPointerSize() in DWA...Konstantin Zhuravlyov2017-04-171-2/+2
* AArch64: support nonlazybindTim Northover2017-04-173-19/+35
* This patch closes PR#32216: Better testing of schedule model instruction late...Andrew V. Tischenko2017-04-141-2/+2
* [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16Adam Nemet2017-04-131-3/+8
* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-122-7/+11
* [AArch64] Fix scheduling info for INS(vector, general) instruction.Balaram Makam2017-04-112-1/+6
* [AArch64] Simplify MacroFusionEvandro Menezes2017-04-111-79/+89
* [ARM/AArch64] Ensure valid vector element types for interleaved accessesMatthew Simpson2017-04-103-10/+39
* [AArch64] Refine Falkor Machine Model - Part 3Balaram Makam2017-04-085-26/+135
* [AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18Petr Hosek2017-04-071-0/+5
* [globalisel][tablegen] Move <Target>InstructionSelector declarations to anony...Daniel Sanders2017-04-065-77/+62
* [AArch64] Crypto requires FP.James Molloy2017-04-051-1/+1
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-55/+37
* [AArch64] Avoid partial register deps on insertelt of load into lane 0.Ahmed Bougacha2017-04-041-11/+5
* [AArch64] Add missing schedinfo, check completeness for Falkor.Balaram Makam2017-04-041-10/+17
* [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsiaPetr Hosek2017-04-046-12/+34
* [AArch64] Refine Falkor Machine Model - Part 2Balaram Makam2017-04-043-92/+454
* [tablegen][globalisel] Add support for nested instruction matching.Daniel Sanders2017-04-041-36/+0
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-033-1/+37
* Revert "Instrument SDISel C++ patterns"Quentin Colombet2017-04-012-369/+355
* Instrument SDISel C++ patternsQuentin Colombet2017-04-012-355/+369
* Reduce the number of times we query the subtarget for the same information.Eric Christopher2017-03-311-5/+4
* Small cleanup to remove extraneous cast.Eric Christopher2017-03-311-2/+1
* [AArch64] Add new subtarget feature to fold LSL into address mode.Balaram Makam2017-03-313-5/+53
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsForTarg...Simon Pilgrim2017-03-312-2/+3
* [AArch64ISelLowering] Remove `else` after `return` in LowerGlobalTLSAddress.Davide Italiano2017-03-301-1/+1
* [AArch64] Simplify isSingExtended()/isZeroExtended(). NFCI.Davide Italiano2017-03-301-10/+4
* [AArch64] [Assembler] option to disable negative immediate conversionsSanne Wouda2017-03-284-10/+30
* [GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.Ahmed Bougacha2017-03-271-2/+2
* [GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.Ahmed Bougacha2017-03-271-0/+5
* [GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.Ahmed Bougacha2017-03-271-1/+19
* [GlobalISel][AArch64] Select store of zero to WZR/XZR.Ahmed Bougacha2017-03-271-0/+11
* [GlobalISel][AArch64] Select CBZ.Ahmed Bougacha2017-03-272-3/+53
* [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.Chad Rosier2017-03-272-2/+12
* [Target] Remove some code probably copy/pasted from another backend.Davide Italiano2017-03-261-4/+0
* [MachineScheduler] Reference the correct header.Davide Italiano2017-03-261-1/+1
* [AArch64] Refine Falkor Machine Model - Part1Balaram Makam2017-03-253-88/+422
* [Outliner] Revert r298734.Jessica Paquette2017-03-241-1/+1
* [Outliner] Remove no red zone requirment for AArch64Jessica Paquette2017-03-241-1/+1
* TTI: Split IsSimple in MemIntrinsicInfoMatt Arsenault2017-03-241-4/+0
* [AArch64] Drive-by cleanup, make this code shorter. NFCI.Davide Italiano2017-03-221-3/+1
* Rename AttributeSet to AttributeListReid Kleckner2017-03-214-6/+6
* [Outliner] ACTUALLY remove the errs outputJessica Paquette2017-03-201-1/+1
* [Outliner] Remove output for offset range checkJessica Paquette2017-03-201-3/+1
* [GlobalISel] Use the correct calling conv for callsDiana Picus2017-03-202-4/+5
* Make library calls sensitive to regparm module flag (Fixes PR3997).Nirav Dave2017-03-182-4/+6
* Capitalize ArgListEntry fields. NFC.Nirav Dave2017-03-182-6/+7
* [Outliner] Add outliner for AArch64Jessica Paquette2017-03-172-11/+303
* [AArch64] Use alias analysis in the load/store optimization pass.Chad Rosier2017-03-171-7/+14
* Remove getArgumentList() in favor of arg_begin(), args(), etcReid Kleckner2017-03-161-2/+1
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