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* MachineCombiner Pass for selecting faster instruction sequence on AArch64Gerolf Hoflehner2014-08-071-0/+6
| | | | | | | | | | Re-commit of r214832,r21469 with a work-around that avoids the previous problem with gcc build compilers The work-around is to use SmallVector instead of ArrayRef of basic blocks in preservesResourceLen()/MachineCombiner.cpp llvm-svn: 215151
* [AArch64] Add a testcase for r214957.James Molloy2014-08-061-1/+8
| | | | llvm-svn: 214965
* Revert "r214832 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-051-6/+0
| | | | | | | It broke compiling of most Benchmark and internal test, as clang got clashed by segmentation fault or assertion. llvm-svn: 214845
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-051-0/+6
| | | | | | | | | | | sequence on AArch64 Re-commit of r214669 without changes to test cases LLVM::CodeGen/AArch64/arm64-neon-mul-div.ll and LLVM:: CodeGen/AArch64/dp-3source.ll This resolves the reported compfails of the original commit. llvm-svn: 214832
* Revert "r214669 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-041-6/+0
| | | | | | This commit broke "make check" for several hours, so get it reverted. llvm-svn: 214697
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | sequence - AArch64 target support This patch turns off madd/msub generation in the DAGCombiner and generates them in the MachineCombiner instead. It replaces the original code sequence with the combined sequence when it is beneficial to do so. When there is no machine model support it always generates the madd/msub instruction. This is true also when the objective is to optimize for code size: when the combined sequence is shorter is always chosen and does not get evaluated. When there is a machine model the combined instruction sequence is evaluated for critical path and resource length using machine trace metrics and the original code sequence is replaced when it is determined to be faster. rdar://16319955 llvm-svn: 214669
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-1/+1
| | | | | | No functionality change. llvm-svn: 213938
* AArch64: remove "arm64_be" support in favour of "aarch64_be".Tim Northover2014-07-231-3/+1
| | | | | | | | | There really is no arm64_be: it was a useful fiction to test big-endian support while both backends existed in parallel, but now the only platform that uses the name (iOS) doesn't have a big-endian variant, let alone one called "arm64_be". llvm-svn: 213748
* AArch64: Re-enable AArch64AddressTypePromotionDuncan P. N. Exon Smith2014-07-021-0/+2
| | | | | | | | | | | This reverts commits r212189 and r212190. While this pass was accidentally disabled (until r212073), r205437 slipped in a use of `auto` that should have been `auto&`. This fixes PR20188. llvm-svn: 212201
* AArch64: Temporarily disable AArch64AddressTypePromotionDuncan P. N. Exon Smith2014-07-021-2/+0
| | | | | | | Temporarily disable AArch64AddressTypePromotion, which was effectively re-enabled in r212073 and r212075, while I look into PR20188. llvm-svn: 212189
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-101-1/+1
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. llvm-svn: 210605
* Move AArch64InstrInfo to AArch64Subtarget.Eric Christopher2014-06-101-2/+1
| | | | llvm-svn: 210599
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-101-1/+1
| | | | llvm-svn: 210557
* Have AArch64SelectionDAGInfo take a DataLayout parameter ratherEric Christopher2014-06-101-1/+1
| | | | | | than a TargetMachine. llvm-svn: 210554
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-101-7/+0
| | | | llvm-svn: 210552
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-101-1/+1
| | | | llvm-svn: 210549
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-101-2/+1
| | | | | | AArch64FrameLowering. llvm-svn: 210548
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-301-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+208
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-121/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-2/+2
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-221-0/+9
| | | | llvm-svn: 206861
* Add AArch64 big endian Target (aarch64_be)Christian Pirker2014-02-241-4/+26
| | | | llvm-svn: 202024
* [AArch64] Add support for TargetTransformInfo Analysis.Chad Rosier2014-02-201-0/+8
| | | | llvm-svn: 201793
* Test commit - remove the new line to ↵Christian Pirker2014-02-191-1/+0
| | | | | | lib/Target/AArch64/AArch64TargetMachine.cpp. llvm-svn: 201698
* Test commit - added a new line to lib/Target/AArch64/AArch64TargetMachine.cpp.Christian Pirker2014-02-191-0/+1
| | | | llvm-svn: 201692
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Make the llvm mangler depend only on DataLayout.Rafael Espindola2014-01-031-1/+1
| | | | | | | | | | | | | | Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. llvm-svn: 198438
* Remove the 's' DataLayout specificationRafael Espindola2014-01-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | During the years there have been some attempts at figuring out how to align byval arguments. A look at the commit log suggests that they were * Use the ABI alignment. * When that was not sufficient for x86-64, I added the 's' specification to DataLayout. * When that was not sufficient Evan added the virtual getByValTypeAlignment. * When even that was not sufficient, we just got the FE to add the alignment to the byval. This patch is just a simple cleanup that removes my first attempt at fixing the problem. I also added an AArch64 implementation of getByValTypeAlignment to make sure this patch is a nop. I also left the 's' parsing for backward compatibility. I will send a short email to llvmdev about the change for anyone maintaining an out of tree target. llvm-svn: 198287
* The preferred alignment defaults to the abi alignment. Omit if it is the same.Rafael Espindola2013-12-161-1/+1
| | | | llvm-svn: 197400
* On DataLayout, omit the default of p:64:64:64.Rafael Espindola2013-12-161-1/+1
| | | | llvm-svn: 197397
* Simplify the datalayout string of ARM and AArch64.Rafael Espindola2013-12-121-1/+1
| | | | | | | | No functionality change. Reviewed by Tim Northover. llvm-svn: 197172
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* AArch64: add branch fixup pass.Tim Northover2013-02-151-0/+1
| | | | | | | | | | | | | This is essentially a stripped-down version of the ConstandIslands pass (which always had these two functions), providing just the features necessary for correctness. In particular there needs to be a way to resolve the situation where a conditional branch's destination block ends up out of range. This issue crops up when self-hosting for AArch64. llvm-svn: 175269
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-151-1/+0
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* AArch64: add block comments where missingTim Northover2013-02-141-0/+3
| | | | | | Only comments affected. No code change at all. llvm-svn: 175169
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+78
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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