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* [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOpDavid Tellenbach2019-11-231-1/+1
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* [AArch64] Fix addressing mode predicatesEvandro Menezes2019-11-121-3/+5
| | | | Fix predicates related to the register offset addressing mode.
* [AArch64] Add new scheduling predicatesEvandro Menezes2019-11-111-0/+70
| | | | Add new scheduling predicates to identify more ASIMD forms.
* [AArch64] Update for ExynosEvandro Menezes2019-05-021-53/+0
| | | | | | Fix the forwarding of multiplication results for Exynos M4. llvm-svn: 359834
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AArch64] Add new scheduling predicatesEvandro Menezes2019-01-031-31/+86
| | | | | | Add new scheduling predicates to identify the ASIMD loads and stores using the post indexed addressing mode. llvm-svn: 350332
* [AArch64] Use canonical copy idiomEvandro Menezes2018-12-191-3/+1
| | | | | | | Use only the canonical form of the alias for register transfers in the `IsCopyIdiomPred` predicate. llvm-svn: 349685
* [AArch64] Simplify the scheduling predicates (NFC)Evandro Menezes2018-12-141-5/+3
| | | | | | | The instruction encodings make it unnecessary to distinguish extended W-form from X-form instructions. llvm-svn: 349185
* [AArch64] Refactor the scheduling predicatesEvandro Menezes2018-12-101-61/+325
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. Augment the number of helper predicates used by processor specific predicates. Differential revision: https://reviews.llvm.org/D55375 llvm-svn: 348768
* [AArch64] Refactor the scheduling predicates (3/3) (NFC)Evandro Menezes2018-11-261-18/+31
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::hasExtendedReg()`. Differential revision: https://reviews.llvm.org/D54822 llvm-svn: 347599
* [AArch64] Refactor the scheduling predicates (2/3) (NFC)Evandro Menezes2018-11-261-30/+55
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::hasShiftedReg()`. Differential revision: https://reviews.llvm.org/D54820 llvm-svn: 347598
* [AArch64] Refactor the scheduling predicates (1/3) (NFC)Evandro Menezes2018-11-261-0/+70
Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::isScaledAddr()` Differential revision: https://reviews.llvm.org/D54777 llvm-svn: 347597
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