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path: root/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
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* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-202/+0
| | | | | | | | | | The previous names were both misleading (the MachineLegalizer actually contained the info tables) and inconsistent with the selector & translator (in having a "Machine") prefix. This should make everything sensible again. The only functional change is the name of a couple of command-line options. llvm-svn: 284287
* [AArch64][MachineLegalizer] Mark more G_BITCAST as legal.Quentin Colombet2016-10-131-1/+8
| | | | | | | Basically any vector types that fits in a 32-bit register is also valid as far as copies are concerned. llvm-svn: 284089
* GlobalISel: mark G_BRCOND on s1 as legal.Tim Northover2016-10-121-3/+2
| | | | | | It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter. llvm-svn: 284070
* [AArch64][MachineLegalizer] Mark more bitcasts as legal.Quentin Colombet2016-10-121-0/+3
| | | | | | Those are copies, we do not have to do any legalization action for them. llvm-svn: 283970
* GlobalISel: support same-size casts on AArch64.Tim Northover2016-10-111-0/+13
| | | | | | | Mostly Ahmed's work again, I'm just sprucing things up slightly before committing. llvm-svn: 283952
* [AArch64][MachineLegalizer] Mark v2s32 G_LOAD as legal.Quentin Colombet2016-10-111-1/+1
| | | | | | | Actually every 64-bit loads are legal, but right now the API does not offer a simple way to express that. llvm-svn: 283829
* GlobalISel: allow G_GLOBAL_VALUEs in AArch64 legalization.Tim Northover2016-10-101-0/+1
| | | | llvm-svn: 283808
* GlobalISel: legalize GEP instructions with small offsets.Tim Northover2016-09-151-0/+6
| | | | llvm-svn: 281602
* GlobalISel: relax type constraints on G_ICMP to allow pointers.Tim Northover2016-09-151-0/+1
| | | | llvm-svn: 281600
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-1/+0
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-151-1/+1
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* GlobalISel: mark pointer stores as legal on AArch64.Tim Northover2016-09-141-1/+1
| | | | llvm-svn: 281448
* GlobalISel: legalize frem to a libcall on AArch64.Tim Northover2016-08-291-0/+3
| | | | llvm-svn: 279988
* GlobalISel: mark G_FPEXT legal from float to double.Tim Northover2016-08-261-0/+3
| | | | llvm-svn: 279845
* GlobalISel: mark G_FCMP legal on float & double.Tim Northover2016-08-261-0/+4
| | | | llvm-svn: 279844
* GlobalISel: simplify G_ICMP legalization regime.Tim Northover2016-08-261-11/+6
| | | | | | | | | | | | | | It's unclear how the old %res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1 is actually different from an s1 verison %res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1 so we'll remove it for now. llvm-svn: 279843
* GlobalISel: legalize sdiv and srem operations.Tim Northover2016-08-261-0/+4
| | | | llvm-svn: 279842
* GlobalISel: legalize under-width divisions.Tim Northover2016-08-261-2/+6
| | | | llvm-svn: 279841
* GlobalISel: mark selects legalTim Northover2016-08-261-0/+6
| | | | llvm-svn: 279840
* GlobalISel: mark float/int conversions legalTim Northover2016-08-261-0/+14
| | | | llvm-svn: 279839
* GlobalISel: mark overflow bit of overflow ops legal.Tim Northover2016-08-251-1/+4
| | | | | | It's expected this will map to NZCV register class and be properly selectable. llvm-svn: 279761
* GlobalISel: mark simple ops legal even on types < 32-bit.Tim Northover2016-08-251-4/+3
| | | | | | | | The 32-bit variants of these operations don't depend on the bits not being operated on, so they also naturally model operations narrower than the actual register width. llvm-svn: 279760
* GlobalISel: mark pointer constants as legal on AArch64.Tim Northover2016-08-251-0/+2
| | | | llvm-svn: 279759
* GlobalISel: perform multi-step legalizationTim Northover2016-08-251-0/+18
| | | | llvm-svn: 279758
* GlobalISel: mark small extends as legal on AArch64Tim Northover2016-08-251-0/+13
| | | | llvm-svn: 279757
* GlobalISel: legalize integer comparisons on AArch64.Tim Northover2016-08-231-0/+13
| | | | | | | Next step is doing both legalizations at the same time! Marvel at GlobalISel's cunning. llvm-svn: 279566
* GlobalISel: legalize conditional branches on AArch64.Tim Northover2016-08-231-0/+6
| | | | llvm-svn: 279565
* GlobalISel: extend legalizer interface to handle multiple types.Tim Northover2016-08-231-14/+21
| | | | | | | | Instructions like G_ICMP have multiple types that may need to be legalized (the boolean output and nearly arbitrary inputs in this case). So the legalizer must be capable of deciding what to do for each of them separately. llvm-svn: 279554
* GlobalISel: mark pointer casts legal on AArch64.Tim Northover2016-08-231-0/+3
| | | | llvm-svn: 279553
* GlobalISel: legalize 1-bit load/store and mark 8/16 bit variants legal on ↵Tim Northover2016-08-231-2/+5
| | | | | | AArch64. llvm-svn: 279548
* GlobalISel: support legalization of G_FCONSTANTsTim Northover2016-08-191-0/+1
| | | | llvm-svn: 279341
* GlobalISel: teach legalizer how to handle integer constants.Tim Northover2016-08-191-0/+9
| | | | llvm-svn: 279340
* [AArch64][GlobalISel] Select floating-point binary ops.Ahmed Bougacha2016-08-181-0/+4
| | | | | | There is no FREM instruction, but the others are straightforward. llvm-svn: 279081
* [AArch64][GlobalISel] Select G_SDIV/G_UDIV.Ahmed Bougacha2016-08-181-1/+1
| | | | | | | | There is no REM instruction; that will require an expansion. It's not obvious that should be done in select, rather than as a (custom?) legalization. llvm-svn: 279074
* [AArch64][GlobalISel] Select (variable) shifts.Ahmed Bougacha2016-08-161-0/+4
| | | | | | For now, no support for immediates. llvm-svn: 278804
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-161-0/+2
| | | | | | And mark it as legal. llvm-svn: 278802
* GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.Tim Northover2016-08-041-1/+1
| | | | | | | These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
* GlobalISel: implement narrowing for G_ADD.Tim Northover2016-08-041-1/+8
| | | | llvm-svn: 277769
* [AArch64][GlobalISel] Mark basic binops/memops as legal.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | | | | We currently use and test these, and select most of them. Mark them as legal even though we don't go through the full ir->asm flow yet. This doesn't currently have standalone tests, but the verifier will soon learn to check that the regbankselect/select tests are legal. llvm-svn: 277471
* GlobalISel: implement legalization pass, with just one transformation.Tim Northover2016-07-221-0/+30
This adds the actual MachineLegalizeHelper to do the work and a trivial pass wrapper that legalizes all instructions in a MachineFunction. Currently the only transformation supported is splitting up a vector G_ADD into one acting on smaller vectors. llvm-svn: 276461
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