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* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-121-1/+1
| | | | | | Machine model description by Dave Estes <cestes@codeaurora.org>. llvm-svn: 260686
* [AArch64] Merge two adjacent str WZR into str XZRJun Bum Lim2016-02-121-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
* [AArch64] Refactoring findMatchingStore() in aarch64-ldst-opt; NFCJun Bum Lim2016-02-111-11/+13
| | | | | | | | | | | | Summary: This change makes findMatchingStore() follow the same coding style introduced in r260275. Reviewers: gberry, junbuml Subscribers: aemerson, rengolin, haicheng, bmakam, mssimpso Differential Revision: http://reviews.llvm.org/D17083 llvm-svn: 260534
* [AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier2016-02-111-11/+68
| | | | | | | | | | | | | This patch allows the mixing of scaled and unscaled load/stores to form load/store pairs. This is a reapplication of r259812, which had an incorrect assert. The test_stur_str_no_assert() test is a reduced version of the issue hit in the AArch64 self-host. PR24465 llvm-svn: 260523
* [AArch64] Refactor is logic into a helper function. NFC.Chad Rosier2016-02-101-12/+22
| | | | llvm-svn: 260419
* [AArch64] Update comment to match reality. NFC.Chad Rosier2016-02-101-2/+2
| | | | llvm-svn: 260406
* [AArch64] This bit of logic is specific to pairing. NFC.Chad Rosier2016-02-101-8/+10
| | | | llvm-svn: 260383
* [AArch64] This check is specific to merging instructions. NFC.Chad Rosier2016-02-091-4/+4
| | | | llvm-svn: 260283
* [AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iteratorGeoff Berry2016-02-091-8/+9
| | | | | | | | | | | | | | | Summary: Fix case where a pre-inc/dec load/store would not be formed if the add/sub that forms the inc/dec part of the operation was the first instruction in the block being examined. Reviewers: mcrosier, jmolloy, t.p.northover, junbuml Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16785 llvm-svn: 260275
* [AArch64] Bail even earlier if the instructions modifieds the base register. ↵Chad Rosier2016-02-091-5/+6
| | | | | | NFC. llvm-svn: 260274
* [AArch64] Simplify. NFC.Chad Rosier2016-02-091-3/+1
| | | | llvm-svn: 260273
* [AArch64] Add an assert to ensure we don't scale an offset that can't be scaled.Chad Rosier2016-02-091-1/+3
| | | | llvm-svn: 260272
* [AArch64] Add a FIXME about invalid KILL markers after the ld/st opt pass.Chad Rosier2016-02-091-0/+5
| | | | llvm-svn: 260264
* [AArch64] Remove redundant calls and clang format. NFC.Chad Rosier2016-02-091-42/+40
| | | | llvm-svn: 260260
* [AArch64] Hoist now common logic. NFC.Chad Rosier2016-02-091-13/+9
| | | | llvm-svn: 260257
* [AArch64] Rename variable to make it clear we're merging here, not pairing.Chad Rosier2016-02-091-19/+19
| | | | llvm-svn: 260256
* [AArch64] Separage the codegen logic for widening vs. pairing. NFC.Chad Rosier2016-02-091-38/+94
| | | | llvm-svn: 260249
* [AArch64] Cleanup to simplify logic when widening vs. pairing loads/stores. NFC.Chad Rosier2016-02-091-13/+50
| | | | | | | | The logic to pair instructions and merge narrow instructions has become cloogy and error prone. This patch beings to unravel these two similar, but distinct optimizations. llvm-svn: 260242
* [AArch64] Rename variable to improve readability. NFC.Chad Rosier2016-02-091-5/+5
| | | | llvm-svn: 260228
* [AArch64] Remove stale comment.Chad Rosier2016-02-091-3/+0
| | | | llvm-svn: 260226
* [AArch64] Refactoring aarch64-ldst-opt. NCF.Jun Bum Lim2016-02-051-25/+38
| | | | | | | Remove narrow load / store instructions from getMatchingPairOpcode(), and add getMatchingWideOpcode(). llvm-svn: 259914
* Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3)."Renato Golin2016-02-051-76/+21
| | | | | | This reverts commit r259812 as it broke AArch64 self-hosting. llvm-svn: 259881
* [AArch64] Bound the number of instructions we scan when searching for updates.Chad Rosier2016-02-041-14/+26
| | | | | | | This only impacts the creation of pre-/post-index instructions. The bound was set high enough such that it did not change code generation for SPEC200X. llvm-svn: 259828
* [AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3).Chad Rosier2016-02-041-21/+76
| | | | | | | | | | | | | | | This patch allows the mixing of scaled and unscaled load/stores to form load/store pairs. PR24465 http://reviews.llvm.org/D12116 Many thanks to Ahmed and Michael for fixes and code review. This is a reapplication of r246769 and r259790. The tramp3d failure was caused by an incorrect refactoring in the patch. Specifically, we weren't always properly clearing the SExtIdx flag. llvm-svn: 259812
* Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR."Chad Rosier2016-02-041-77/+22
| | | | | | This reverts commit r259790. tramp3d-v4 is still having problems. llvm-svn: 259795
* [AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier2016-02-041-22/+77
| | | | | | | | | | | | | | This patch allows the mixing of scaled and unscaled load/stores to form load/store pairs. PR24465 http://reviews.llvm.org/D12116 Many thanks to Ahmed and Michael for fixes and code review. This is a reapplication of r246769, which was reverted in r246782 due to a test-suite failure. I'm unable to reproduce the issue at this time. llvm-svn: 259790
* [AArch64] Add a FIXME comment.Chad Rosier2016-02-021-0/+2
| | | | llvm-svn: 259515
* [AArch64] Allocate the modified and used regs only once per function.Chad Rosier2016-02-021-12/+17
| | | | llvm-svn: 259510
* Move comments a bit closer to associated code. NFC.Chad Rosier2016-02-011-29/+25
| | | | llvm-svn: 259411
* [AArch64] Set MMOs on pre- and post-index instructions.Chad Rosier2016-01-281-2/+4
| | | | | | | Without the MMOs the MI scheduler is unable to reason about the dependencies of these instructions. llvm-svn: 259052
* [AArch64] Remove a bunch of useless FIXME comments.Chad Rosier2016-01-191-4/+0
| | | | llvm-svn: 258193
* [AArch64] Remove more dead code after r258093.Chad Rosier2016-01-191-12/+4
| | | | llvm-svn: 258191
* [AArch64] Remove unused arguments. NFC.Chad Rosier2016-01-181-7/+7
| | | | | | AFAICT, these have been unused since the initial backend import. llvm-svn: 258093
* Update to use new name alignTo().Rui Ueyama2016-01-141-1/+1
| | | | llvm-svn: 257804
* Extract helper function to merge MemoryOperand lists [NFC]Philip Reames2016-01-061-22/+4
| | | | | | | | | | In the discussion on http://reviews.llvm.org/D15730, Andy pointed out we had a utility function for merging MMO lists. Since it turned we actually had two copies and there's another review in progress (http://reviews.llvm.org/D15230) which needs the same, extract it into a utility function and clean up the interfaces to make it easier to use with a MachineInstBuilder. I introduced a pair here to track size and allocation together. I think we should probably move in the direction of the MachineOperandsRef helper class, but I'm leaving that for further work. I want to get the poison state introduced before I make major changes to the interface. Differential Revision: http://reviews.llvm.org/D15757 llvm-svn: 256909
* [AArch64] Promote loads from storedJun Bum Lim2015-12-221-3/+280
| | | | | | | | | | | | | | | | | | | | This is a recommit of r256004 which was reverted in r256160. The issue was the incorrect promotion for half and byte loads transformed into mov instructions. This fix will replace half and byte type loads only with bit field extracts. Original commit message: This change promotes load instructions which directly read from stored by replacing them with mov instructions. If the store is wider than the load, the load will be replaced with a bitfield extract. For example : STRWui %W1, %X0, 1 %W0 = LDRHHui %X0, 3 becomes STRWui %W1, %X0, 1 %W0 = UBFMWri %W1, 16, 31 llvm-svn: 256249
* Revert "[AArch64] Promote loads from stores"Jun Bum Lim2015-12-211-280/+3
| | | | | | This reverts commit r256004 due to a failure in cortex-a53. llvm-svn: 256160
* [AArch64] Promote loads from storesJun Bum Lim2015-12-181-3/+280
| | | | | | | | | | | | | | This change promotes load instructions which directly read from stores by replacing them with mov instructions. If the store is wider than the load, the load will be replaced with a bitfield extract. For example : STRWui %W1, %X0, 1 %W0 = LDRHHui %X0, 3 becomes STRWui %W1, %X0, 1 %W0 = UBFMWri %W1, 16, 31 llvm-svn: 256004
* [AArch64]Merge narrow zero stores to a wider storeJun Bum Lim2015-11-201-16/+80
| | | | | | | | | | | | | This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
* [AArch64] Refactoring aarch64-ldst-opt. NCF.Jun Bum Lim2015-11-191-16/+13
| | | | | | | | | Summary : * Rename isSmallTypeLdMerge() to isNarrowLoad(). * Rename NumSmallTypeMerged to NumNarrowTypePromoted. * Use Subtarget defined as a member variable. llvm-svn: 253587
* [AArch64]Extend merging narrow loads into a wider loadJun Bum Lim2015-11-191-26/+107
| | | | | | | | | | | | | | This change extends r251438 to handle more narrow load promotions including byte type, unscaled, and signed. For example, this change will convert : ldursh w1, [x0, #-2] ldurh w2, [x0, #-4] into ldur w2, [x0, #-4] asr w1, w2, #16 and w2, w2, #0xffff llvm-svn: 253577
* [AArch64] Fix halfword load merging for big-endian targetsOliver Stannard2015-11-101-3/+9
| | | | | | | | | | | | For big-endian targets, when we merge two halfword loads into a word load, the order of the halfwords in the loaded value is reversed compared to little-endian, so the load-store optimiser needs to swap the destination registers. This does not affect merging of two word loads, as we use ldp, which treats the memory as two separate 32-bit words. llvm-svn: 252597
* [AArch64]Enable the narrow ld promotion only on profitable microarchitecturesJun Bum Lim2015-11-061-8/+22
| | | | | | | | | The benefit from converting narrow loads into a wider load (r251438) could be micro-architecturally dependent, as it assumes that a single load with two bitfield extracts is cheaper than two narrow loads. Currently, this conversion is enabled only in cortex-a57 on which performance benefits were verified. llvm-svn: 252316
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-271-45/+216
| | | | | | | | | | | | | | | | This recommits r250719, which caused a failure in SPEC2000.gcc because of the incorrect insert point for the new wider load. Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 251438
* Revert "[AArch64]Merge halfword loads into a 32-bit load"James Molloy2015-10-231-215/+45
| | | | | | This reverts commit r250719. This introduced a codegen fault in SPEC2000.gcc, when compiled for Cortex-A53. llvm-svn: 251108
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-191-45/+215
| | | | | | | | | | | | | Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 250719
* [AArch64] Deprecate a command-line option used for testing.Chad Rosier2015-10-011-12/+4
| | | | | | | Support for pairing unscaled loads and stores has been enabled since the original ARM64 port. This feature is no longer experimental, AFAICT. llvm-svn: 249049
* [AArch64] Hoist commonly failing check. NFC.Chad Rosier2015-10-011-6/+6
| | | | llvm-svn: 249011
* [AArch64] Rename variable to improve readability. NFC.Chad Rosier2015-10-011-10/+10
| | | | llvm-svn: 249008
* [AArch64] Update comment to reflect reality.Chad Rosier2015-10-011-2/+2
| | | | llvm-svn: 249007
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