bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[AArch64] Delete two empty files, which should be removed by r239713.	Hao Liu	2015-06-15	1	-0/+0
\| \| \| \|	llvm-svn: 239715
*	[AArch64] Revert r239711 again. We need to discuss how to share code between ↵	Hao Liu	2015-06-15	1	-392/+0
\| \| \| \| \| \|	AArch64 and ARM backend. llvm-svn: 239713
*	[AArch64] Match interleaved memory accesses into ldN/stN instructions.	Hao Liu	2015-06-15	1	-0/+392
\| \| \| \| \| \| \|	Re-commit after adding "-aarch64-neon-syntax=generic" to fix the failure on OS X. This patch was firstly committed in r239514, then reverted in r239544 because of a syntax incompatible failure on OS X. llvm-svn: 239711
*	This reverts commit r239529 and r239514.	Rafael Espindola	2015-06-11	1	-392/+0
\| \| \| \| \| \| \| \| \|	Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions." Revert "Fixing MSVC 2013 build error." The test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X. llvm-svn: 239544
*	Fixing MSVC 2013 build error.	Aaron Ballman	2015-06-11	1	-0/+1
\| \| \| \|	llvm-svn: 239529
*	[AArch64] Match interleaved memory accesses into ldN/stN instructions.	Hao Liu	2015-06-11	1	-0/+391
	Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true" E.g. Transform an interleaved load (Factor = 2): %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements Into: %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr) %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0 %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1 E.g. Transform an interleaved store (Factor = 2): %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7> ; Interleaved vec store <8 x i32> %i.vec, <8 x i32>* %ptr Into: %v0 = shuffle %i.vec, undef, <0, 1, 2, 3> %v1 = shuffle %i.vec, undef, <4, 5, 6, 7> call void aarch64.neon.st2(%v0, %v1, %ptr) llvm-svn: 239514