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* [globalisel][tablegen] Move <Target>InstructionSelector declarations to ↵Daniel Sanders2017-04-061-74/+0
| | | | | | | | | | | | | | | | anonymous namespaces Summary: This resolves the issue of tablegen-erated includes in the headers for non-GlobalISel builds in a simpler way than before. Reviewers: qcolombet, ab Reviewed By: ab Subscribers: igorb, ab, mgorny, dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30998 llvm-svn: 299637
* [GlobalISel][AArch64] Select CBZ.Ahmed Bougacha2017-03-271-3/+6
| | | | | | | | | | CBZ/CBNZ represent a substantial portion of all conditional branches. Look through G_ICMP to select them. We can't use tablegen yet because the existing patterns match an AArch64ISD node. llvm-svn: 298856
* [globalisel] LLVM_BUILD_GLOBAL_ISEL=OFF should prevent GlobalISel ↵Daniel Sanders2017-03-141-0/+3
| | | | | | instruction selector from being declared. llvm-svn: 297786
* [globalisel][tblgen] Add support for ComplexPatternsDaniel Sanders2017-03-141-0/+11
| | | | | | | | | | | | | | | | | | | Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
* GlobalISel: select G_VASTART on iOS AArch64.Tim Northover2017-02-081-0/+8
| | | | | | | The AAPCS ABI is substantially more complicated so that's coming in a separate patch. For now we can generate correct code for iOS though. llvm-svn: 294493
* [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-061-3/+5
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 291197
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-211-0/+4
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-101-1/+5
| | | | llvm-svn: 283809
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+39
And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
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