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path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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* [AArch64] Disable LDP/STP for quadsEvandro Menezes2016-04-131-0/+14
* [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCompareInstr to pre...Evgeny Astigeevich2016-04-061-57/+99
* [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()Jun Bum Lim2016-03-311-1/+1
* [AArch64] Replace return 0 with return false. NFC.Chad Rosier2016-03-231-3/+3
* [AArch64] Add a helpful assert. NFC.Chad Rosier2016-03-211-0/+1
* [AArch64] Fix a -Wdocumentation warning. NFC.Chad Rosier2016-03-211-2/+2
* [AArch64] Enable more load clustering in the MI Scheduler.Chad Rosier2016-03-181-7/+111
* [AArch64] Optimize compare and branch sequence when the compare's constant o...Balaram Makam2016-03-101-25/+82
* [AArch64] Move helper functions into TII, so they can be reused elsewhere. NFC.Chad Rosier2016-03-091-0/+29
* [AArch64] Minor cleanup/remove redundant code. NFC.Chad Rosier2016-03-091-11/+7
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-4/+3
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-4/+4
* Remove uses of builtin comma operator.Richard Trieu2016-02-181-12/+24
* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-121-1/+2
* Remove extra semicolon. NFC.Chad Rosier2016-02-011-1/+1
* [AArch64 MachineCombine] Enhance/Add support for general reassociation to red...Haicheng Wu2016-01-071-10/+47
* replace MachineCombinerPattern namespace and enum with enum class; NFCISanjay Patel2015-11-051-32/+32
* [Machine Combiner] Refactor machine reassociation code to be target-independent.Chad Rosier2015-09-211-1/+0
* [AArch64] Reorder cases to improve readability. NFC.Chad Rosier2015-09-181-9/+9
* [AArch64] Remove some redundant cases. NFC.Chad Rosier2015-09-181-16/+8
* [AArch64] Match FI+offset in STNP addressing mode.Ahmed Bougacha2015-09-101-0/+13
* [MIR Serialization] static -> static const in getSerializable*MachineOperandT...Hal Finkel2015-08-301-2/+2
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-181-0/+31
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-111-2/+2
* test commit, only added one spaceLawrence Hu2015-07-231-1/+1
* This patch eanble register coalescing to coalesce the following:Weiming Zhao2015-07-231-0/+14
* AArch64: Restrict macroop fusion heuristics to cyclone.Matthias Braun2015-07-201-31/+33
* AArch64: Add aditional Cyclone macroop fusion opportunitiesMatthias Braun2015-07-201-16/+34
* Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstrBenjamin Kramer2015-06-251-16/+6
* name change: hasPattern() -> getMachineCombinerPatterns() ; NFCSanjay Patel2015-06-191-16/+16
* [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.Sanjoy Das2015-06-151-8/+8
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-4/+4
* [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFCKeno Fischer2015-06-081-4/+3
* Use new MachineInstr mayLoadOrStore() API.Chad Rosier2015-05-211-4/+2
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-1/+1
* [AArch64] Fix invalid use of references to BuildMI.James Molloy2015-04-161-3/+3
* Revert "Migrate the AArch64 TargetRegisterInfo to its TargetMachine"Eric Christopher2015-03-181-32/+31
* Migrate the AArch64 TargetRegisterInfo to its TargetMachineEric Christopher2015-03-121-31/+32
* Remove the need to cache the subtarget in the AArch64 TargetRegisterInfoEric Christopher2015-03-121-1/+1
* ArrayRefize memory operand folding. NFC.Benjamin Kramer2015-02-281-4/+4
* Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.Eric Christopher2015-01-281-3/+2
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-1/+1
* [AArch64] Don't optimize all compare instructions.Juergen Ributzka2014-11-181-26/+51
* [AArch64] Keep flags on condition vreg when instantiating a CB branch.Ahmed Bougacha2014-11-071-1/+2
* [AArch64] Use the correct register class for ORR.Juergen Ributzka2014-11-041-1/+1
* Remove unused variable.Eric Christopher2014-10-151-1/+0
* [AArch64] Wrong CC access in CSINC-conditional branch sequenceGerolf Hoflehner2014-10-141-5/+1
* [AAarch64] Optimize CSINC-branch sequenceGerolf Hoflehner2014-10-141-29/+136
* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-011-6/+5
* Revert r218778 while investigating buldbot breakage.Adrian Prantl2014-10-011-5/+6
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