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path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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* [AArch64] Support for FP FMA when -ffp-contract=fastEvandro Menezes2016-09-151-3/+5
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-2/+2
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-4/+23
* [AArch64] Support stackmap/patchpoint in getInstSizeInBytesDiana Picus2016-09-131-4/+21
* CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MIDuncan P. N. Exon Smith2016-09-111-3/+3
* Typo fixes. NFCDiana Picus2016-08-311-1/+1
* Make some LLVM_CONSTEXPR variables const. NFC.George Burgess IV2016-08-251-1/+1
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-2/+4
* [AArch64] Re-factor code shared by AArch64LoadStoreOpt and AArch64InstrInfo.Geoff Berry2016-08-121-30/+5
* Move helpers into anonymous namespaces. NFC.Benjamin Kramer2016-08-061-0/+2
* AArch64: Assert on branch displacement bitsMatt Arsenault2016-08-021-0/+7
* AArch64: BranchRelaxtion cleanupsMatt Arsenault2016-08-021-0/+50
* [AArch64] Return the correct size for TLSDESC_CALLSEQDiana Picus2016-08-011-0/+3
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-2/+2
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-2/+2
* Typo fix. NFCDiana Picus2016-07-271-1/+1
* [AArch64] Cleanup sign extend in genAlternativeCodeSequenceDavid Majnemer2016-07-211-3/+3
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-5/+5
* [AArch64] Set COPY ZR isAsCheapAsAMove when needed.Haicheng Wu2016-07-151-2/+6
* s/constexpr/LLVM_CONSTEXPR in AArch64InstrInfo.cpp.Justin Lebar2016-07-141-1/+1
* [CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.Justin Lebar2016-07-141-15/+7
* [CodeGen] Refactor MachineMemOperand's Flags enum.Justin Lebar2016-07-141-1/+2
* [AArch64] Set FMOVS0 and FMOVD0 as isAsCheapAsAMove when needed.Haicheng Wu2016-07-121-0/+6
* AArch64: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-7/+6
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-180/+177
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-12/+14
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-021-10/+9
* Delete AArch64II::MO_CONSTPOOL.Rafael Espindola2016-05-311-2/+1
* AArch64: Fix indentationMatthias Braun2016-05-281-9/+9
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-271-4/+4
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-101-1/+2
* [AArch64] Combine callee-save and local stack SP adjustment instructions.Geoff Berry2016-05-061-0/+3
* [AArch64] Add cheap as move instructions for Exynos M1Evandro Menezes2016-05-041-2/+33
* AArch64/optimizeCondBranch: Remove earlier kill flag when forming TBZMatthias Braun2016-05-031-0/+2
* Cleanup comments. NFC.Chad Rosier2016-05-021-2/+3
* Re-apply r267206 with a fix for the encoding problem: when the immediate ofQuentin Colombet2016-04-251-3/+14
* [MachineCombiner] Support for floating-point FMA on ARM64 (re-commit r267098)Gerolf Hoflehner2016-04-241-35/+545
* Revert "[AArch64] Fix optimizeCondBranch logic."Renato Golin2016-04-231-5/+5
* [AArch64] Fix optimizeCondBranch logic.Quentin Colombet2016-04-221-5/+5
* [AArch64] When creating MRS instruction, make sure the destination register isQuentin Colombet2016-04-221-2/+1
* Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64Daniel Sanders2016-04-221-545/+35
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-221-35/+545
* [AArch64][CodeGen] Fix of PR27158: incorrect peephole optimization in AArch64...Evgeny Astigeevich2016-04-211-73/+155
* [AArch64] Add load/store pair instructions to getMemOpBaseRegImmOfsWidth().Chad Rosier2016-04-151-5/+46
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-3/+13
* [AArch64] Disable LDP/STP for quadsEvandro Menezes2016-04-131-0/+14
* [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCompareInstr to pre...Evgeny Astigeevich2016-04-061-57/+99
* [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()Jun Bum Lim2016-03-311-1/+1
* [AArch64] Replace return 0 with return false. NFC.Chad Rosier2016-03-231-3/+3
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