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path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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* Revert "Merge memtag instructions with adjacent stack slots."Evgenii Stepanov2020-01-081-2/+0
* Merge memtag instructions with adjacent stack slots.Evgenii Stepanov2020-01-081-0/+2
* [MachineOutliner][AArch64] Save + restore LR in noreturn functionsJessica Paquette2020-01-071-1/+11
* Lower TAGPstack with negative offset to SUBG.Evgenii Stepanov2020-01-061-1/+8
* [AArch64] Enable clustering memory accesses to fixed stack objectsJay Foad2019-12-181-39/+68
* Fix assertion failure in getMemOperandWithOffsetWidthKristof Beyls2019-12-171-3/+5
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-161-8/+304
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Oliver Stannard2019-12-111-288/+8
* [AArch64] Fix issues with large arrays on stackKiran Chandramohan2019-12-101-1/+1
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-7/+65
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-091-65/+7
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-7/+65
* [AArch64] Fix MUL/SUB fusingSanne Wouda2019-12-051-20/+90
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-051-8/+288
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Sterling Augustine2019-12-041-284/+8
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-041-8/+284
* [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADDSanne Wouda2019-12-031-0/+352
* [AArch64][DebugInfo] Fix incorrect call site param value produced by MOVZXiDjordje Todorovic2019-11-141-1/+1
* [AArch64] Extend storeRegToStackSlot to spill SVE registers.Sander de Smalen2019-11-131-0/+23
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-12/+12
* Reland: [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-11-081-19/+11
* Revert "[AArch64][MachineOutliner] Return address signing for outlined functi...Oliver Stannard2019-11-011-241/+7
* Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional destin...Simon Pilgrim2019-10-311-11/+19
* [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-10-311-19/+11
* [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-10-301-7/+241
* [ARM][AArch64][DebugInfo] Improve call site instruction interpretationDjordje Todorovic2019-10-301-0/+48
* [AArch64] Fix offset calculationShoaib Meenai2019-10-161-3/+3
* [AArch64] Stackframe accesses to SVE objects.Sander de Smalen2019-10-141-3/+36
* fix fmls fp16Sebastian Pop2019-10-081-12/+41
* [AArch64] Static (de)allocation of SVE stack objects.Sander de Smalen2019-10-031-2/+29
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-1/+1
* [SVE][Inline-Asm] Add constraints for SVE predicate registersKerry McLaughlin2019-09-161-0/+11
* [AArch64] MachineCombiner FMA matching. NFC.Sjoerd Meijer2019-09-131-325/+112
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-8/+31
* [aarch64] Add combine patterns for fp16 fmlaSebastian Pop2019-09-071-62/+280
* [SVE][Inline-Asm] Support for SVE asm operandsKerry McLaughlin2019-09-021-0/+10
* Revert Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero f...Paul Walker2019-08-171-6/+4
* Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta...Paul Walker2019-08-171-4/+6
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instru...Paul Walker2019-08-161-6/+4
* Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta...Paul Walker2019-08-161-4/+6
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instru...Paul Walker2019-08-161-6/+4
* Add missing MIR serialization text for AArch64II::MO_TAGGED.Evgeniy Stepanov2019-08-151-3/+6
* [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-26/+26
* [AArch64][WinCFI] Do not pair callee-save instructions in LoadStoreOptimizerSander de Smalen2019-08-071-0/+12
* [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets.Sander de Smalen2019-08-061-65/+83
* [AArch64] NFC: Add generic StackOffset to describe scalable offsets.Sander de Smalen2019-08-061-8/+12
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-30/+26
* AArch64: Add a tagged-globals backend feature.Peter Collingbourne2019-07-311-1/+2
* SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned ...Peter Collingbourne2019-07-311-1/+1
* Basic codegen for MTE stack tagging.Evgeniy Stepanov2019-07-171-0/+17
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