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path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-1/+1
* [SVE][Inline-Asm] Add constraints for SVE predicate registersKerry McLaughlin2019-09-161-0/+11
* [AArch64] MachineCombiner FMA matching. NFC.Sjoerd Meijer2019-09-131-325/+112
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-8/+31
* [aarch64] Add combine patterns for fp16 fmlaSebastian Pop2019-09-071-62/+280
* [SVE][Inline-Asm] Support for SVE asm operandsKerry McLaughlin2019-09-021-0/+10
* Revert Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero f...Paul Walker2019-08-171-6/+4
* Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta...Paul Walker2019-08-171-4/+6
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instru...Paul Walker2019-08-161-6/+4
* Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta...Paul Walker2019-08-161-4/+6
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instru...Paul Walker2019-08-161-6/+4
* Add missing MIR serialization text for AArch64II::MO_TAGGED.Evgeniy Stepanov2019-08-151-3/+6
* [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-26/+26
* [AArch64][WinCFI] Do not pair callee-save instructions in LoadStoreOptimizerSander de Smalen2019-08-071-0/+12
* [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets.Sander de Smalen2019-08-061-65/+83
* [AArch64] NFC: Add generic StackOffset to describe scalable offsets.Sander de Smalen2019-08-061-8/+12
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-30/+26
* AArch64: Add a tagged-globals backend feature.Peter Collingbourne2019-07-311-1/+2
* SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned ...Peter Collingbourne2019-07-311-1/+1
* Basic codegen for MTE stack tagging.Evgeniy Stepanov2019-07-171-0/+17
* [SystemZ, RegAlloc] Favor 3-address instructions during instruction selection.Jonas Paulsson2019-06-081-1/+1
* [AArch64] check for INLINEASM_BR along w/ INLINEASMNick Desaulniers2019-05-241-2/+5
* [DebugInfo][AArch64] Recognise target specific instruction as mov instrAlexey Lapshin2019-05-221-0/+25
* [AArch64] only indicate CFI on Windows if we emitted CFIMandeep Singh Grang2019-05-151-5/+12
* [AArch64] Add support for MTE intrinsicsJaved Absar2019-04-231-0/+16
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-13/+13
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-1/+1
* [AArch64] NFC: Cleanup isAArch64FrameOffsetLegalSander de Smalen2019-03-271-200/+98
* [AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfoSander de Smalen2019-03-271-0/+6
* AArch64: implement copy for paired GPR registers.Tim Northover2019-02-071-0/+41
* [AArch64][Outliner] Don't outline BTI instructionsOliver Stannard2019-02-051-0/+8
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] Emit the correct MCExpr relocations specifiers like VK_ABS_G0, etcMandeep Singh Grang2019-01-101-1/+2
* Initial AArch64 SLH implementation.Kristof Beyls2019-01-091-0/+5
* Introduce control flow speculation tracking pass for AArch64Kristof Beyls2018-12-181-0/+7
* [AArch64] Refactor the Exynos scheduling predicatesEvandro Menezes2018-12-101-208/+1
* [AArch64] Fix Exynos predicateEvandro Menezes2018-12-061-8/+10
* Fix -Wparentheses warning. NFCI.Simon Pilgrim2018-12-041-3/+2
* [MachineOutliner] Move stack instr check logic to getOutliningCandidateInfoJessica Paquette2018-12-041-96/+72
* [MachineOutliner][AArch64][NFC] Add early exit to candidate discarding logicJessica Paquette2018-12-041-0/+6
* [MachineOutliner] Drop candidates that require fixups if it's beneficialJessica Paquette2018-12-031-5/+24
* [MachineOutliner][AArch64] Improve checks for stack instructionsJessica Paquette2018-12-011-1/+23
* [MachineOutliner] Outline both register save calls + no LR save calls togetherJessica Paquette2018-11-301-32/+26
* [MachineScheduler] Order FI-based memops based on stack directionFrancis Visoiu Mistrih2018-11-291-5/+8
* [MachineScheduler] Add support for clustering mem ops with FI base operandsFrancis Visoiu Mistrih2018-11-281-23/+77
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-32/+49
* [TableGen] Refactor macro names (NFC)Evandro Menezes2018-11-271-1/+1
* [AArch64] Refactor the scheduling predicates (3/3) (NFC)Evandro Menezes2018-11-261-27/+0
* [AArch64] Refactor the scheduling predicates (2/3) (NFC)Evandro Menezes2018-11-261-38/+0
* [AArch64] Refactor the scheduling predicates (1/3) (NFC)Evandro Menezes2018-11-261-61/+3
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