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path: root/llvm/lib/Target/AArch64/AArch64InstrFormats.td
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* AArch64: Implement conditional compare sequence matching.Matthias Braun2015-07-161-29/+48
* [AArch64] Fix problems in decoding generic MSR instructionsPetr Pavlu2015-07-151-0/+3
* [AArch64] Implement add/adds/sub/subs/cmp/cmn with negative immediate aliasesArnaud A. de Grandmaison2015-07-011-6/+43
* Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."Matthias Braun2015-06-171-48/+29
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-021-0/+172
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-011-29/+48
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-6/+7
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-7/+6
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-6/+7
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-161-0/+4
* [AArch64] Allow non-standard INS/DUP encodingsBradley Smith2015-04-141-3/+3
* [AArch64] Add a comment to make it explicit why we increased the complexity.Quentin Colombet2015-04-021-0/+4
* [AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extensionVladimir Sukharev2015-03-311-0/+199
* [AArch64] Fix poor codegen for add immediate.Quentin Colombet2015-03-311-0/+2
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-1/+1
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-011-7/+5
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-271-0/+4
* [AArch64] Fix registerAllocator assigns same register for base and wback inQuentin Colombet2014-08-111-7/+6
* MachineCombiner Pass for selecting faster instruction sequence on AArch64Gerolf Hoflehner2014-08-071-2/+3
* Revert "r214832 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-051-3/+2
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-051-2/+3
* Revert "r214669 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-041-3/+2
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-031-2/+3
* Implement AArch64 TTI interface isAsCheapAsAMove.Jiangning Liu2014-07-291-3/+5
* Port memory barriers intrinsics to AArch64Yi Kong2014-07-171-2/+8
* AArch64: add support for llvm.aarch64.hint intrinsicSaleem Abdulrasool2014-07-121-11/+17
* [AArch64] Add logical alias instructions to MC AsmParserArnaud A. de Grandmaison2014-07-101-10/+39
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-101-0/+6
* [AArch64] Missing aliases for CMP/CMN [W]SP with no shiftArtyom Skrobov2014-06-091-0/+4
* [AArch64] Fix the ordering of the accumulate operand in SchedRW list.Chad Rosier2014-06-091-3/+3
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+8574
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-1487/+0
* AArch64: error when both positional & named operands are used.Tim Northover2014-03-131-3/+1
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+79
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-0/+19
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-121-0/+28
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-061-0/+18
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+18
* Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.Jiangning Liu2013-11-051-0/+44
* Implement AArch64 post-index vector load/store multiple N-element structure c...Hao Liu2013-11-051-0/+26
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-0/+19
* [AArch64] Make the use of FP instructions optional, but enabled by default.Amara Emerson2013-10-311-0/+4
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-171-0/+18
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-101-0/+18
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-101-18/+0
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-101-0/+18
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+16
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-0/+19
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-041-17/+30
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-2/+19
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