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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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* AArch64: Implement conditional compare sequence matching.Matthias Braun2015-07-161-0/+7
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-091-1/+2
* Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT userMehdi Amini2015-07-091-1/+1
* Make isLegalAddressingMode() taking DataLayout as an argumentMehdi Amini2015-07-091-2/+2
* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+1
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+2
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-051-6/+3
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch...Hao Liu2015-06-261-0/+9
* Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."Matthias Braun2015-06-171-7/+0
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-011-0/+7
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-2/+4
* Change getTargetNodeName() to produce compiler warnings for missing cases, fi...Matthias Braun2015-05-071-1/+1
* AArch64: Don't lower ISD::SELECT to ISD::SELECT_CCMatthias Braun2015-04-071-0/+3
* [AArch64] Enable the codegenprepare optimization that promotes operation to formQuentin Colombet2015-03-311-0/+2
* [aarch64] Distinguish the 'Q' and 'm' inline assembly memory constraints.Daniel Sanders2015-03-231-2/+6
* Make each target map all inline assembly memory constraints to InlineAsm::Con...Daniel Sanders2015-03-161-0/+6
* [AArch64] Avoid going through GPRs for across-vector instructions.Ahmed Bougacha2015-03-101-0/+12
* Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how ...JF Bastien2015-03-041-1/+2
* Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot ...Kristof Beyls2015-03-041-5/+5
* getRegForInlineAsmConstraint wants to use TargetRegisterInfo forEric Christopher2015-02-261-1/+2
* Rewrite the global merge pass to be subprogram agnostic for now.Eric Christopher2015-02-231-4/+0
* Prevent hoisting fmul from THEN/ELSE to IF if there is fmsub/fmadd opportunity.Chad Rosier2015-02-231-0/+3
* Remove getSubtargetImpl from AArch64ISelLowering and cache theEric Christopher2015-01-291-1/+2
* fix typos; NFCSanjay Patel2015-01-281-1/+1
* Add missing 'override' keyword.Craig Topper2014-11-281-1/+1
* AArch64: treat [N x Ty] as a block during procedure calls.Tim Northover2014-11-271-0/+4
* DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same di...Hao Liu2014-11-211-0/+1
* [AArch64] Generate vector signed/unsigned mul and mla/mls long.Chad Rosier2014-10-081-0/+3
* constify TargetMachine parameter.Eric Christopher2014-10-031-1/+1
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-171-0/+1
* AArch64: fix big-endian immediate materialisationTim Northover2014-09-041-0/+7
* Refactor AtomicExpandPass and add a generic isAtomic() method to InstructionRobin Morisset2014-09-031-1/+3
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
* Fix typos in comments, NFCRobin Morisset2014-08-291-2/+1
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-271-3/+4
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+1
* [AArch64] Lower sdiv x, pow2 using add + select + shift.Chad Rosier2014-07-231-0/+3
* [codegen,aarch64] Add a target hook to the code generator to controlChandler Carruth2014-07-031-0/+3
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-101-1/+1
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+464
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-410/+0
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-161-4/+0
* Implement global merge optimization for global variables.Jiangning Liu2014-05-151-0/+4
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-111-1/+1
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-111-1/+1
* Implememting named register intrinsicsRenato Golin2014-05-061-0/+2
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-22/+26
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-221-0/+4
* This commit enables unaligned memory accesses of vector types on AArch64 back...Jiangning Liu2014-04-181-0/+6
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