| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Move AArch64TargetLowering to AArch64Subtarget. | Eric Christopher | 2014-06-10 | 1 | -1/+1 |
| * | [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift | Chad Rosier | 2014-06-09 | 1 | -9/+9 |
| * | [C++11] Use 'nullptr'. | Craig Topper | 2014-06-08 | 1 | -1/+1 |
| * | AArch64: mark small types (i1, i8, i16) as promoted | Tim Northover | 2014-06-03 | 1 | -9/+7 |
| * | [AArch64] Correctly deal with VPR stack parameter passing. | Jiangning Liu | 2014-06-03 | 1 | -3/+10 |
| * | Have the TLOF creation take a Triple rather than needing a subtarget. | Eric Christopher | 2014-05-31 | 1 | -3/+3 |
| * | Fix an assertion failure caused by v1i64 in DAGCombiner Shrink. | Hao Liu | 2014-05-29 | 1 | -16/+9 |
| * | AArch64: force i1 to be zero-extended at an ABI boundary. | Tim Northover | 2014-05-26 | 1 | -0/+12 |
| * | AArch64: simplify calling conventions slightly. | Tim Northover | 2014-05-26 | 1 | -29/+28 |
| * | AArch64/ARM64: move ARM64 into AArch64's place | Tim Northover | 2014-05-24 | 1 | -0/+7926 |
| * | AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. | Tim Northover | 2014-05-24 | 1 | -5564/+0 |
| * | SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bs... | Benjamin Kramer | 2014-05-19 | 1 | -0/+2 |
| * | Target: remove old constructors for CallLoweringInfo | Saleem Abdulrasool | 2014-05-17 | 1 | -5/+5 |
| * | Revert "Implement global merge optimization for global variables." | Rafael Espindola | 2014-05-16 | 1 | -14/+0 |
| * | Implement global merge optimization for global variables. | Jiangning Liu | 2014-05-15 | 1 | -0/+14 |
| * | Pass the value type to TLI::getRegisterByName | Hal Finkel | 2014-05-11 | 1 | -1/+2 |
| * | Implememting named register intrinsics | Renato Golin | 2014-05-06 | 1 | -0/+12 |
| * | AArch64: Mark vector long multiplication as expand. | Benjamin Kramer | 2014-04-29 | 1 | -0/+5 |
| * | Convert SelectionDAG::getMergeValues to use ArrayRef. | Craig Topper | 2014-04-27 | 1 | -2/+2 |
| * | Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer an... | Craig Topper | 2014-04-26 | 1 | -3/+2 |
| * | Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. | Craig Topper | 2014-04-26 | 1 | -15/+9 |
| * | [C++] Use 'nullptr'. Target edition. | Craig Topper | 2014-04-25 | 1 | -8/+8 |
| * | Add 'musttail' marker to call instructions | Reid Kleckner | 2014-04-24 | 1 | -0/+4 |
| * | [AArch64] Enable global merge pass. | Jiangning Liu | 2014-04-22 | 1 | -0/+7 |
| * | [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE | Chandler Carruth | 2014-04-22 | 1 | -1/+2 |
| * | This is one of the optimizations ported from ARM64 to AArch64 to address the ... | Jiangning Liu | 2014-04-18 | 1 | -0/+2 |
| * | This commit enables unaligned memory accesses of vector types on AArch64 back... | Jiangning Liu | 2014-04-18 | 1 | -0/+44 |
| * | Convert SelectionDAG::getVTList to use ArrayRef | Craig Topper | 2014-04-16 | 1 | -2/+2 |
| * | Break PseudoSourceValue out of the Value hierarchy. It is now the root of its... | Nick Lewycky | 2014-04-15 | 1 | -1/+1 |
| * | [AArch64] Implement the isLegalAddressingMode and getScalingFactorCost APIs. | Chad Rosier | 2014-04-12 | 1 | -0/+66 |
| * | [AArch64] Implement the isZExtFree APIs. | Chad Rosier | 2014-04-09 | 1 | -0/+36 |
| * | [AArch64] Implement the isTruncateFree API. | Chad Rosier | 2014-04-09 | 1 | -0/+21 |
| * | ARM64: handle v1i1 types arising from setcc properly. | Tim Northover | 2014-04-04 | 1 | -28/+0 |
| * | Make consistent use of MCPhysReg instead of uint16_t throughout the tree. | Craig Topper | 2014-04-04 | 1 | -2/+2 |
| * | [AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS | Logan Chien | 2014-03-27 | 1 | -0/+88 |
| * | AArch64_BE function argument passing for ARM ABI | Christian Pirker | 2014-03-26 | 1 | -2/+11 |
| * | AArch64: fix LowerCONCAT_VECTORS for new CodeGen. | Tim Northover | 2014-03-10 | 1 | -10/+11 |
| * | [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. | Benjamin Kramer | 2014-03-02 | 1 | -8/+4 |
| * | AArch64: __va_list.__stack must be 8-byte aligned | Oliver Stannard | 2014-02-20 | 1 | -1/+3 |
| * | [AArch64] Expanded sin, cos, pow with FP vector types inputs | Ana Pazos | 2014-02-18 | 1 | -0/+10 |
| * | Fix a typo about lowering AArch64 va_copy. | Jiangning Liu | 2014-02-18 | 1 | -1/+1 |
| * | [AArch64 NEON] Fix a bug to avoid using floating type as condition type in lo... | Kevin Qin | 2014-02-14 | 1 | -11/+6 |
| * | [AArch64]Fix the assertion failure caused by "v1i1 SETCC" DAG node. | Hao Liu | 2014-02-14 | 1 | -0/+90 |
| * | [AArch64] Custom lower concat_vector patterns with v4i16, v4i32, v8i8, v8i16,... | Chad Rosier | 2014-01-30 | 1 | -0/+53 |
| * | [AArch64 NEON] Lower SELECT_CC with vector operand. | Kevin Qin | 2014-01-29 | 1 | -56/+178 |
| * | [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SH... | Kevin Qin | 2014-01-27 | 1 | -28/+90 |
| * | Revert r199791. | Kevin Qin | 2014-01-27 | 1 | -85/+28 |
| * | fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 ... | Kevin Qin | 2014-01-23 | 1 | -4/+4 |
| * | [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SH... | Kevin Qin | 2014-01-22 | 1 | -28/+85 |
| * | [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT. | Kevin Qin | 2014-01-21 | 1 | -15/+21 |
