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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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* Add op_values() to iterate over the SDValue operands of an SDNode.Pete Cooper2015-06-261-2/+1
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch...Hao Liu2015-06-261-0/+154
* Fix "the the" in comments.Eric Christopher2015-06-191-2/+2
* Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."Matthias Braun2015-06-171-178/+36
* Clean up redundant copies of Triple objects. NFCDaniel Sanders2015-06-161-1/+1
* [AArch64] Generalize extract-high DUP extension to MOVI/MVNI.Ahmed Bougacha2015-06-161-15/+24
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-011-36/+178
* Re-commit of r238201 with fix for building with shared libraries.Luke Cheeseman2015-06-011-1/+2
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-3/+5
* Revert "Re-commit changes in r237579 with fix for bug breaking windows builds."Diego Novillo2015-05-261-2/+1
* Re-commit changes in r237579 with fix for bug breaking windows builds.Luke Cheeseman2015-05-261-1/+2
* [opaque pointer type] Allow gep_type_iterator to work with the pointee type f...David Blaikie2015-05-211-0/+1
* Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced ini...David Blaikie2015-05-181-5/+5
* Revert r237579, as it broke windows buildbotsOliver Stannard2015-05-181-2/+1
* [LLVM - ARM/AArch64] Add ACLE special register intrinsicsOliver Stannard2015-05-181-1/+2
* Mark SMIN/SMAX/UMIN/UMAX nodes as legal and add patterns for them.James Molloy2015-05-151-0/+6
* Re-apply r237247 - [AArch64] Codegen VMAX/VMIN for safe math casesArtyom Skrobov2015-05-141-41/+74
* Revert r237247 - [AArch64] Codegen VMAX/VMIN.. as it is causing failures in S...Silviu Baranga2015-05-131-72/+40
* [AArch64] Codegen VMAX/VMIN for safe math casesArtyom Skrobov2015-05-131-40/+72
* ScheduleDAGInstrs: In functions with tail calls PseudoSourceValues are not no...Arnold Schwaighofer2015-05-081-1/+3
* Change getTargetNodeName() to produce compiler warnings for missing cases, fi...Matthias Braun2015-05-071-3/+4
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-228/+256
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-256/+228
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-228/+256
* [AArch64] Also combine vector selects fed by non-i1 SETCCs.Ahmed Bougacha2015-04-271-3/+15
* [AArch64] Don't assert when combining (v3f32 select (setcc f64)).Ahmed Bougacha2015-04-271-0/+6
* [AArch64] Handle vec4, vec8, vec16 *itofp for halfPirama Arumuga Nainar2015-04-231-0/+10
* [AArch64] Avoid vector->load dependency cycles when creating LD1*post.Ahmed Bougacha2015-04-171-0/+7
* [AArch64] Don't assert on f16 in DUP PerfectShuffle generator.Ahmed Bougacha2015-04-161-1/+1
* Allow memory intrinsics to be tail callsKrzysztof Parzyszek2015-04-131-3/+4
* [AArch64] Promote f16 operations to f32.Ahmed Bougacha2015-04-101-8/+50
* [AArch64] Remove redundant -march option. Also fix a think-o from r234462.Lang Hames2015-04-091-1/+1
* [AArch64] Teach AArch64TargetLowering::getOptimalMemOpType to consider alignmentLang Hames2015-04-091-1/+11
* AArch64: Don't lower ISD::SELECT to ISD::SELECT_CCMatthias Braun2015-04-071-44/+57
* [AArch64] Enable the codegenprepare optimization that promotes operation to formQuentin Colombet2015-03-311-0/+54
* Refactor: Simplify boolean expressions in AArch64 targetDavid Blaikie2015-03-241-2/+2
* [AArch64] Prefer UZP for concat_vector of illegal truncs.Ahmed Bougacha2015-03-211-16/+12
* Fix bug while building FP16 constant vectors for AArch64Pirama Arumuga Nainar2015-03-171-2/+4
* Appease AArch64ISelLowering.cpp miscompiled by g++-4.7.2.NAKAMURA Takumi2015-03-171-0/+6
* [AArch64] Use intermediate step for concat_vectors of illegal truncs.Ahmed Bougacha2015-03-171-0/+31
* [AArch64] Factor out N->getOperand()s; format. NFCI.Ahmed Bougacha2015-03-171-13/+12
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-111-3/+3
* [AArch64] Avoid going through GPRs for across-vector instructions.Ahmed Bougacha2015-03-101-0/+27
* Make static variables const if possible. Makes them go into a read-only section.Benjamin Kramer2015-03-081-6/+2
* Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how ...JF Bastien2015-03-041-2/+4
* Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot ...Kristof Beyls2015-03-041-95/+61
* [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).Chad Rosier2015-03-031-9/+9
* Convert push_back loops into append calls.Benjamin Kramer2015-02-281-8/+5
* getRegForInlineAsmConstraint wants to use TargetRegisterInfo forEric Christopher2015-02-261-2/+3
* Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.Eric Christopher2015-02-261-1/+1
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