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* [AArch64] Remove dead code.Tilmann Scheller2014-06-161-3/+0
| | | | | | Both function declarations lack a callee and an implementation. llvm-svn: 211029
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+3035
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-1576/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-3/+3
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+1
| | | | llvm-svn: 207377
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-6/+6
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [AArch64 NEON]Implment loading vector constant form constant pool.Kevin Qin2013-12-181-9/+0
| | | | llvm-svn: 197551
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-120/+469
| | | | llvm-svn: 195078
* Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-181-18/+168
| | | | | | The functions are like: vst1_s8_x2 ... llvm-svn: 194990
* AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-11-141-3/+1
| | | | llvm-svn: 194679
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-0/+99
| | | | llvm-svn: 194648
* AArch64: refactor vector list creation to be more uniformTim Northover2013-11-111-101/+55
| | | | | | | | | | | Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a special register-class to deal with the constraints, and C++ code to support selection. However, that C++ code can be made reasonably uniform to simplify the selection process. Hence this patch. No functionality change, so no tests. llvm-svn: 194361
* Implement AArch64 post-index vector load/store multiple N-element structure ↵Hao Liu2013-11-051-13/+191
| | | | | | | | | | | | class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 194043
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+298
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-101-298/+0
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. llvm-svn: 192354
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+298
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192352
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-0/+1
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* AArch64: fix even more JIT failuresTim Northover2013-07-251-3/+3
| | | | | | | The last patch corrected some issues, but constant-pool entries had actual codegen bugs in the large memory model (which MCJIT uses). llvm-svn: 187126
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-011-2/+3
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. llvm-svn: 185360
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-071-8/+8
| | | | | | These objects are internal to the TargetMachine object and may change. llvm-svn: 183485
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-6/+6
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-6/+6
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* AArch64: support literal pool access in large memory model.Tim Northover2013-05-041-20/+48
| | | | llvm-svn: 181120
* AArch64: implement large code model access to global variables.Tim Northover2013-05-041-0/+9
| | | | | | | | | | | | | | The MOVZ/MOVK instruction sequence may not be the most efficient (a literal-pool load could be better) but adding that would require reinstating the ConstantIslands pass. For now the sequence is correct, and that's enough. Beware, as of commit GNU ld does not appear to support the relocations needed for this. Its primary purpose (for now) will be to support JITed code, since in that case there is no guarantee of where your code will end up in memory relative to external symbols it references. llvm-svn: 181117
* AArch64: remove barriers from AArch64 atomic operations.Tim Northover2013-04-081-0/+106
| | | | | | | | I've managed to convince myself that AArch64's acquire/release instructions are sufficient to guarantee C++11's required semantics, even in the sequentially-consistent case. llvm-svn: 179005
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-151-77/+69
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* Fix formatting in AArch64 backend.Tim Northover2013-02-051-4/+5
| | | | | | | | | | | This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. llvm-svn: 174370
* Remove cyclic dependency in AArch64 librariesTim Northover2013-02-051-1/+1
| | | | | | | | This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. llvm-svn: 174369
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+422
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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