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path: root/llvm/lib/Support/TargetParser.cpp
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* Support: catch invalid accessesSaleem Abdulrasool2016-03-051-2/+2
| | | | | | | | | | | It is possible to invoke these methods on an invalid input resulting in an invalid substring construction. It seems that we do not have unit tests for these methods. Tests to ensure that the invalid call is caught to follow in clang. Resolves PR26839. llvm-svn: 262778
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-151-0/+6
| | | | llvm-svn: 257878
* Reordering fields to reduce padding in LLVM. NFCBen Craig2015-12-141-4/+4
| | | | llvm-svn: 255554
* [ARM] Add ARMv8.2-A to TargetParserOliver Stannard2015-12-011-0/+3
| | | | | | | | | | | | Add ARMv8.2-A to TargetParser, so that it can be used by the clang command-line options and the .arch directive. Most testing of this will be done in clang, checking that the command-line options that this enables work. Differential Revision: http://reviews.llvm.org/D15037 llvm-svn: 254400
* Handle ARMv6-J as an alias, instead of fake architectureArtyom Skrobov2015-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: This follows D14577 to treat ARMv6-J as an alias for ARMv6, instead of an architecture in its own right. The functional change is that the default CPU when targeting ARMv6-J changes from arm1136j-s to arm1136jf-s, which is currently used as the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs. The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't affect code generation, attributes, optimizations, or anything else, apart from selecting the default CPU. Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14755 llvm-svn: 253675
* TargetParser.cpp: Fixup -- StringRef::startswith() is better here. NFC.NAKAMURA Takumi2015-11-191-1/+1
| | | | llvm-svn: 253570
* llvm/lib/Support/TargetParser.cpp: Rework llvm::ARM::getArchExtFeature() to ↵NAKAMURA Takumi2015-11-191-3/+7
| | | | | | avoid abuse of Twine in r253470. llvm-svn: 253566
* [ARM] Add +feature names to TargetParser extensions tableBradley Smith2015-11-181-1/+17
| | | | llvm-svn: 253470
* Handle ARMv6KZ namingArtyom Skrobov2015-11-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
* NFC refactorings in lib/Support/TargetParser.cppArtyom Skrobov2015-11-161-16/+16
| | | | | | | | | | | | | | | | Summary: * declare FPUNames, ARCHNames, ARCHExtNames, HWDivNames, CPUNames as static const * implement getDefaultExtensions with a StringSwitch, in the same way getDefaultFPU is implemented Reviewers: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14648 llvm-svn: 253201
* [ARM] Allow TargetParser to accurately target architecturesBradley Smith2015-11-161-5/+14
| | | | | | | | | | | | Instead of defaulting to an empty string, we want to default to the CPU 'generic' in the case of no valid default CPU being found, (as long as the architecture is actually valid). In order to do this we add a default FPU for each architecture, as well as falling back to architecture defaults for extensions and FPU in the case of a generic CPU is specified. llvm-svn: 253198
* Cull non-standard variants of ARM architectures (NFC)Artyom Skrobov2015-11-121-13/+5
| | | | | | | | | | | | | | | Summary: This patch changes ARMV5, ARMV5E, ARMV6SM, ARMV6HL, ARMV7, ARMV7L, ARMV7HL, ARMV7EM to be treated as aliases for the corresponding standard architectures, instead of as actual architectures. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14577 llvm-svn: 252903
* ARM: support .watchos_version_min and .tvos_version_min.Tim Northover2015-10-281-0/+1
| | | | | | | | These MachO file directives are used by linkers and other tools to provide compatibility information, much like the existing .ios_version_min and .macosx_version_min. llvm-svn: 251569
* [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-devArtyom Skrobov2015-10-231-2/+2
| | | | llvm-svn: 251125
* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-241-0/+5
| | | | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248519
* Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"James Molloy2015-09-211-3/+0
| | | | | | | | This was committed without the code review (http://reviews.llvm.org/D12937) being approved. This reverts commit r248152. llvm-svn: 248174
* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-211-0/+3
| | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following review comments, also updating the description of FeatureDSPThumb2 in ARM.td. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248152
* Added arch extensions and default target features in TargetParser.Alexandros Lamprineas2015-09-051-5/+30
| | | | | Differential: http://reviews.llvm.org/D11590 llvm-svn: 246930
* Remove a linear walk to find the default FPU for a given CPU by directlyChandler Carruth2015-08-301-7/+6
| | | | | | expanding the .def file within a StringSwitch. llvm-svn: 246377
* Teach the target parsing framework to directly compute the length of allChandler Carruth2015-08-301-41/+68
| | | | | | | | | | of its strings when expanding the string literals from the macros, and push all of the APIs to be StringRef instead of C-string APIs. This (remarkably) removes a very non-trivial number of strlen calls. It even deletes code and complexity from one of the primary users -- Clang. llvm-svn: 246374
* Refactor the ARM target parsing to use a def file with macros to expandChandler Carruth2015-08-301-164/+14
| | | | | | | | | | | | | | the necessary tables. This will allow me to restructure the code and structures using this to be significantly more efficient. It also removes the duplication of the list of several enumerators. It also enshrines that the order of enumerators match the order of the entries in the tables, something the implementation code actually uses. No functionality changed (yet). llvm-svn: 246370
* [Triple] Use clang-format to normalize the formatting of the ARM targetChandler Carruth2015-08-301-36/+35
| | | | | | | | | | | | | parsing logic prior to making substantial changes to it. This parsing logic is incredibly wasteful, so I'm planning to rewrite it. Just unittesting the triple parsing logic spends well over 80% of its time in the ARM parsing logic, and others have measured significant time spent here in real production compiles. Stay tuned... llvm-svn: 246369
* [Triple] Stop abusing a class to have only static methods and just useChandler Carruth2015-08-301-27/+27
| | | | | | | the namespace that we are already using for the enums that are produced by the parsing. llvm-svn: 246367
* [ARM] Fix MachO CPU Subtype selectionVedant Kumar2015-08-211-1/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D12040 llvm-svn: 245744
* Revert "[ARM] Fix MachO CPU Subtype selection"Renato Golin2015-08-141-2/+0
| | | | | | This reverts commit r245081, as it breaks many builds. llvm-svn: 245086
* [ARM] Fix MachO CPU Subtype selectionVedant Kumar2015-08-141-0/+2
| | | | | | | | | | This patch makes the Darwin ARM backend take advantage of TargetParser. It also teaches TargetParser about ARMV7K for the first time. This makes target triple parsing more consistent across llvm. Differential Revision: http://reviews.llvm.org/D11996 llvm-svn: 245081
* - Added support for parsing HWDiv features using Target Parser.Alexandros Lamprineas2015-07-271-18/+76
| | | | | | | - Architecture extensions are represented as a bitmap. Phabricator: http://reviews.llvm.org/D11457 llvm-svn: 243335
* Edited the CPUNames table of TargetParserAlexandros Lamprineas2015-07-171-3/+1
| | | | | | | | | - Changed the default FPU of cortex-m4. - Removed "cortex-m4f" entry. Currently not supported. Change-Id: I73121e358aa9e7ba68eb001c2143df390ff2352a Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242528
* - TargetParser does not handle armv7l in parseArchProfile().Alexandros Lamprineas2015-07-161-0/+1
| | | | | | | | - ARM V7L matches the 'A' profile of ARM architecture. Change-Id: I80c8b973f5c93fb040c177a227644d56b1b83ea8 Phabricator: http://reviews.llvm.org/D11261 llvm-svn: 242406
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-151-84/+95
| | | | | | | | -Implemented as a table lookup. Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242284
* Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9Alexandros Lamprineas2015-07-141-96/+83
| | | | | | | | Revert "-Added API for retrieving the default FPU of a CPU from TargetParser." This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669. llvm-svn: 242147
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-141-83/+96
| | | | | | | | -Implemented as a table lookup. Change-Id: Ibf7217f6bd2769e9c06835a5aede3d072dee6757 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242141
* [ARM]: Extend -mfpu options for half-precision and vfpv3xdJaved Absar2015-06-291-2/+0
| | | | | | | | removing default label in switch as it results. This is part of earlier commit http://reviews.llvm.org/D1064 Subscribers: llvm-commits llvm-svn: 240932
* [ARM]: Extend -mfpu options for half-precision and vfpv3xdJaved Absar2015-06-291-23/+37
| | | | | | | | | | | | | | | Some of the the permissible ARM -mfpu options, which are supported in GCC, are currently not present in llvm/clang.This patch adds the options: 'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16. These are related to half-precision floating-point and single precision. Reviewers: rengolin, ranjeet.singh Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10645 llvm-svn: 240930
* [ARM] Disabling vfp4 should disable fp16John Brawn2015-06-121-1/+5
| | | | | | | | | | | ARMTargetParser::getFPUFeatures should disable fp16 whenever it disables vfp4, as otherwise something like -mcpu=cortex-a7 -mfpu=none leaves us with fp16 enabled (though the only effect that will have is a wrong build attribute). Differential Revision: http://reviews.llvm.org/D10397 llvm-svn: 239599
* TargetParser: Fix comments in enum(s) introduced in r239150. [-Wdocumentation]NAKAMURA Takumi2015-06-061-1/+1
| | | | llvm-svn: 239211
* [TargetParser] Properly attach functions of ARMTargetParser to the classBenjamin Kramer2015-06-051-6/+2
| | | | llvm-svn: 239158
* [ARM] Add support for -sp- FPUs and FPU none to TargetParserJohn Brawn2015-06-051-3/+5
| | | | | | | | | | These are added mainly for the benefit of clang, but this also means that they are now allowed in .fpu directives and we emit the correct .fpu directive when single-precision-only is used. Differential Revision: http://reviews.llvm.org/D10238 llvm-svn: 239151
* [ARM] Add knowledge of FPU subtarget features to TargetParserJohn Brawn2015-06-051-15/+110
| | | | | | | | | | | | | Add getFPUFeatures to TargetParser, which gets the list of subtarget features that are enabled/disabled for each FPU, and use it when handling the .fpu directive. No functional change in this commit, though clang will start behaving differently once it starts using this. Differential Revision: http://reviews.llvm.org/D10237 llvm-svn: 239150
* [ARMTargetParser] Follow-up for r239099: one case was missedArtyom Skrobov2015-06-051-1/+1
| | | | llvm-svn: 239147
* Simplify ARMTargetParser::getArchSynonymArtyom Skrobov2015-06-041-10/+9
| | | | | | | | | | | | | | | | Summary: 1) The only caller, ARMTargetParser::parseArch, uses the results for an "endswith" test; so, including the "arm" prefix into the result is unnecessary. 2) Most ARMTargetParser::parseArch callers pass it the output from ARMTargetParser::getCanonicalArchName; so, make this behaviour the default. Then, including the "arm" prefix into the cases is unnecessary. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10249 llvm-svn: 239099
* [ARMTargetParser] Move IAS arch ext parser. NFCRenato Golin2015-05-301-1/+7
| | | | | | | | | | | The plan was to move the whole table into the already existing ArchExtNames but some fields depend on a table-generated file, and we don't yet have this feature in the generic lib/Support side. Once the minimum target-specific table-generated files are available in a generic fashion to these libraries, we'll have to keep it in the ASM parser. llvm-svn: 238651
* [ARMTargetParser] Adding sub-arch information for Clang. NFCRenato Golin2015-05-281-34/+44
| | | | llvm-svn: 238429
* [ARMTargetParser] Adding a few more CPUs for Clang CPU detection. NFC.Renato Golin2015-05-281-14/+22
| | | | llvm-svn: 238415
* Fix comments in ARMTargetParser. NFC.Renato Golin2015-05-281-2/+2
| | | | llvm-svn: 238404
* ARMTargetParser: Normalising build attributesRenato Golin2015-05-271-18/+22
| | | | | | | | | | | | | | | Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu strings are using ARMTargetParser, it's time to make it a bit more conforming with what the ABI says. This commit adds some clarification on what build attributes are accepted and which are "non-standard". It also makes clear that the "defaultCPU" and "defaultArch" methods were really just build attribute getters. It also diverges from GCC's behaviour to say that armv2/armv3 are really an ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4. llvm-svn: 238344
* Reinforce ARMTargetParser::getCanonicalArchName validationRenato Golin2015-05-221-14/+20
| | | | | | | | | | | | | Before, getCanonicalArchName was relying on parseArch() to validate the arch name, which was a problem when other methods, that also needed to call it, were duplicating the steps. But to dissociate getCanonicalArchName from parseArch, we needed to make getCanonicalArchName more robust in detecting valid arch names. It's still not perfect, but will do for the time being, until we merge Triple with TargetParser into a TargetDescription mega class. llvm-svn: 238047
* Adding profile and version parsers to ARMTargetParserRenato Golin2015-05-221-0/+70
| | | | | | | This allows us to match armv6m to default to thumb, but will also be used by Clang's driver and remove the current incomplete copy in it. llvm-svn: 238036
* Make Triple::parseARMArch use ARMTargetParserRenato Golin2015-05-211-1/+46
| | | | | | | | | | | Simplifying Triple::parseARMArch, leaving all the parsing to ARMTargetParser. This commit also adds AArch64 detection to ARMTargetParser canonicalization, and a two RedHat arch names (v{6,7}hl, meaning hard-float / little-endian). Adding enough unit tests to cover the basics. Clang checks fine. llvm-svn: 237902
* Get Triple::getARMCPUForArch() to use TargetParserRenato Golin2015-05-201-25/+178
| | | | | | | | | | | | | | | | | | | | First ARMTargetParser FIXME, conservatively changing the way we parse CPUs in the back-end. Still not perfect, with a lot of special cases, but moving towards a more generic solution. Moving all logic to the target parser made some unwritten assumptions about architectures in Clang to break. I've added a lot of architectures required by Clang, and default to CPUs that Clang believes it should (and I agree). I've also added a lot of unit tests, with the correct CPU for each architecture, and Clang seems to be working correctly, too. It also became clear that using "unsigned ID" as the argument for the get methods makes it hard to know what ID, so I also changed the argument names to match the enum type names. llvm-svn: 237797
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