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* [X86] Use 'unsigned' instead of 'unsigned int' for consistency in the X86 ↵Craig Topper2017-07-081-7/+7
| | | | | | portion of Host.cpp. llvm-svn: 307463
* [X86] Cleanup some CPUID usage in getAvailableFeatures.Craig Topper2017-07-081-5/+10
| | | | | | We should make sure leaf 1 is available before accessing it. Same with leaf 0x80000001. llvm-svn: 307462
* [Support] sys::getProcessTriple should return a macOS triple usingAlex Lorenz2017-07-071-1/+2
| | | | | | | | | | | | | | | the system's version of macOS sys::getProcessTriple returns LLVM_HOST_TRIPLE, whose system version might not be the actual version of the system on which the compiler running. This commit ensures that, for macOS, sys::getProcessTriple returns a triple with the system's macOS version. rdar://33177551 Differential Revision: https://reviews.llvm.org/D34446 llvm-svn: 307372
* [LLVM][X86][Goldmont] Adding new target-cpu: GoldmontMichael Zuckerman2017-06-291-1/+9
| | | | | | | | | | | | | | | | [LLVM SIDE] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. zvi 3. delena 4. RKSimon 5. craig.topper Differential Revision: https://reviews.llvm.org/D34504 llvm-svn: 306658
* [X86] Fixing VPOPCNTDQ feature set lookup.Oren Ben Simhon2017-05-281-1/+1
| | | | llvm-svn: 304086
* [X86] Adding vpopcntd and vpopcntq instructionsOren Ben Simhon2017-05-251-0/+1
| | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq). Differential Revision: https://reviews.llvm.org/D33169 llvm-svn: 303858
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-031-0/+1
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-031-1496/+1495
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-031-1495/+1496
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [Support] Fix ErrorOr assertion when /proc/cpuinfo doesn't exist.Teresa Johnson2017-04-131-0/+1
| | | | | | | | | | | | | | The ErrorOr should not be dereferenced on the error path. Patch by Jacob Young Reviewers: tejohnson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32032 llvm-svn: 300267
* Remove xgene1 from host detectionYi Kong2017-04-111-11/+1
| | | | | | | | | This is not a supported mcpu tuning option. We should treat it as "generic" variant. Also, add record for cortex-a35. llvm-svn: 300003
* Implement host CPU detection for AArch64Yi Kong2017-04-041-4/+32
| | | | | | | | | | | | | | | | | | This shares detection logic with ARM(32), since AArch64 capable CPUs may also run in 32-bit system mode. We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where they report all CPU cores as one single model, depending on which CPU core the kernel is running on. As a workaround, we hardcode the known CPU part name for these SoCs. For big.LITTLE systems, this patch would only return the part name of the first core (usually the little core). Proper support will be added in a follow-up change. Differential Revision: D31675 llvm-svn: 299458
* Make naming in Host.h in line with coding standards.Kristof Beyls2017-03-311-6/+6
| | | | | | | Based on post-commit review comments by Chandler Carruth on https://reviews.llvm.org/D31236. Thanks! llvm-svn: 299211
* Revert "Make naming in Host.h in line with coding standards."Kristof Beyls2017-03-301-6/+6
| | | | | | | | | | | | | | | | | | | This reverts r299062, which caused build failures on Windows. It also reverts the attempts to fix the windows builds in r299064 and r299065. The introduction of namespace llvm::sys::detail makes MSVC, and seemingly also mingw, complain about ambiguity with the existing namespace llvm::detail. E.g.: C:\b\slave\sanitizer-windows\llvm\include\llvm/Support/MathExtras.h(184): error C2872: 'detail': ambiguous symbol C:\b\slave\sanitizer-windows\llvm\include\llvm/Support/PointerLikeTypeTraits.h(31): note: could be 'llvm::detail' C:\b\slave\sanitizer-windows\llvm\include\llvm/Support/Host.h(80): note: or 'llvm::sys::detail' In r299064 and r299065 I tried to fix these ambiguities, based on the errors reported in the log files. It seems however that the build stops early when this kind of error is encountered, and many build-then-fix-iterations on Windows may be needed to fix this. Therefore reverting r299062 for now to get the build working again on Windows. llvm-svn: 299066
* Make naming in Host.h in line with coding standards.Kristof Beyls2017-03-301-6/+6
| | | | | | | Based on post-commit review comments by Chandler Carruth on https://reviews.llvm.org/D31236. Thanks! llvm-svn: 299062
* Refactor getHostCPUName to allow testing on non-native hardware.Kristof Beyls2017-03-301-214/+204
| | | | | | | | | | | | | | | | | | | | | | | | | This refactors getHostCPUName so that for the architectures that get the host cpu info on linux from /proc/cpuinfo, the /proc/cpuinfo parsing logic is present in the build, even if it wasn't built on a linux system for that architecture. Since the code is present in the build, we can then test that code also on other systems, i.e. we don't need to have buildbots setup for all architectures on linux to be able to test this. Instead, developers will test this as part of the regression test run. As an example, a few unit tests are added to test getHostCPUName for ARM running linux. A unit test is preferred over a lit-based test, since the expectation is that in the future, the functionality here will grow over what can be tested with "llc -mcpu=native". This is a preparation step to enable implementing the range of improvements discussed on PR30516, such as adding AArch64 support, support for big.LITTLE systems, reducing code duplication. Differential Revision: https://reviews.llvm.org/D31236 llvm-svn: 299060
* [X86] Remove the HLE feature flag.Craig Topper2017-02-091-1/+0
| | | | | | We only implemented it for one of the 3 HLE instructions and that instruction is also under the RTM flag. Clang only implements the RTM flag from its command line. llvm-svn: 294562
* [X86] Remove INVPCID and SMAP feature flags. They aren't currently used by ↵Craig Topper2017-02-091-2/+0
| | | | | | | | any instructions and not tested. If we implement intrinsics for their instructions in the future, the feature flags can be added back with proper testing. llvm-svn: 294561
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-091-0/+4
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-081-1/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
* [X86] Add Intel Kaby Lake model numbers to getHostCPUName aliased to ↵Craig Topper2017-01-051-2/+4
| | | | | | | | "skylake" since there are no feature differences. Model numbers found here http://www.sandpile.org/x86/cpuid.htm llvm-svn: 291086
* [X86] Change getHostCPUName to report Intel model 0x4e as "skylake" instead ↵Craig Topper2017-01-051-3/+11
| | | | | | | | | | | | | | | | | | | of "skylake-avx512". Add the proper 0x55 model for "skylake-avx512". Summary: Intel's i5-6300U CPU is reporting to have a model id of 78 (4e). The Host detection assumes that to be Skylake Xeon (with AVX512 support), instead of a normal Skylake machine. Patch by: Valentin Churavy Reviewers: nalimilan, craig.topper Subscribers: hfinkel, tkelman, craig.topper, nalimilan, llvm-commits Differential Revision: https://reviews.llvm.org/D28221 llvm-svn: 291084
* [PowerPC] Add identification for POWER8NVLNemanja Ivanovic2017-01-041-0/+1
| | | | | | | This CPU type was not previously recognized by LLVM which led to emitting poor (and sometimes incorrect) code in some JIT workloads on such a machine. llvm-svn: 290961
* Add computeHostNumPhysicalCores() implementation for DarwinMehdi Amini2016-10-191-0/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D25800 llvm-svn: 284656
* Reduce global namespace pollution. NFC.Benjamin Kramer2016-10-181-2/+2
| | | | llvm-svn: 284521
* Add interface to compute number of physical cores on host systemTeresa Johnson2016-10-131-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For now I have only added support for x86_64 Linux, but other systems can be added incrementally. This is to be used for setting the default parallelism for ThinLTO backends (instead of thread::hardware_concurrency which includes hyperthreading and is too aggressive). I'll send this as a follow-on patch, and it will fall back to hardware_concurrency when the new getHostNumPhysicalCores returns -1 (when not supported for a given host system). I also added an interface to MemoryBuffer to force reading a file as a stream - this is required for /proc/cpuinfo which is a special file that looks like a normal file but appears to have 0 size. The existing readers of this file in Host.cpp are reading the first 1024 or so bytes from it, because the necessary info is near the top. But for the new functionality we need to be able to read the entire file. I can go back and change the other readers to use the new getFileAsStream as a follow-on patch since it seems much more robust. Added a unittest. Reviewers: mehdi_amini Subscribers: beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25564 llvm-svn: 284138
* [cpu-detection] Copy simplified version of get_cpuid_max to remove ↵Alina Sbirlea2016-10-041-5/+37
| | | | | | | | | | | | | | | | | dependency to clang's implementation Summary: Attempting to fix PR30384. Take the same approach as in compiler_rt and add a simplified version of __get_cpuid_max. Including cpuid.h is no longer needed. Reviewers: echristo, joerg Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D24597 llvm-svn: 283265
* Properly ifdef the use of cpuid.Alina Sbirlea2016-07-201-1/+6
| | | | llvm-svn: 276156
* [cpu-detection] Cleanup of Host.cpp.Alina Sbirlea2016-07-201-46/+48
| | | | | | | | | | | | | | Summary: Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model. x86 methods are still returning a bool. Reviewers: llvm-commits, echristo, craig.topper, sanjoy Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D22480 llvm-svn: 276149
* [Support] Make helper function static. NFC.Benjamin Kramer2016-07-101-2/+2
| | | | llvm-svn: 275017
* Reapply 272328 and 272329 as a single patch.Alina Sbirlea2016-06-091-10/+3
| | | | | | | | | | | | | | | | | | | | [cpu-detection] [amdfam10] Return barcelona, and amdfam10 for all other subtypes. Address Bug 28067. Along with the refactoring of Host.cpp, getHostCPUName() was modified to return more precise types for CPUs in amdfam10. However, callers of getHostCPUName() do string matching on type, so this cannot be modified. Currently there is support in the x86 backend for barcelona. For all other subtypes the assumed return value is amdfam10. Fix: getHostCPUName() returns barcelona subtype and amdfam10 for all others. This can be extended further when support for the other subtypes is added. Differential revision: http://reviews.llvm.org/D21193 llvm-svn: 272333
* Revert 272328 and 272329 to recommit as a single patch.Alina Sbirlea2016-06-091-3/+10
| | | | llvm-svn: 272332
* Keep barcelona subtype for amdfam10Alina Sbirlea2016-06-091-1/+3
| | | | llvm-svn: 272329
* [cpu-detection] Return amdfam10 for all subtypes. Address Bug 28067.Alina Sbirlea2016-06-091-9/+0
| | | | | | | | | | | | Summary: Remove architecture subtype from the string returned by getHostCPUName(). String matching done on type. Reviewers: llvm-commits, echristo Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21193 llvm-svn: 272328
* [cpu-detection] Add missing break statements in outer switchesAlina Sbirlea2016-06-091-6/+9
| | | | | | | | | | | | Summary: Break on all switch cases for outer and inner switches. No functionality changed. Reviewers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D21158 llvm-svn: 272228
* [cpu-detection] Substantial refactor of Host CPU detection code (x86)Alina Sbirlea2016-06-061-261/+650
| | | | | | | | | | | | | | | | | | Summary: Following D20970 (committed as r271726). This is a substantial refactoring of the host CPU detection code. There is no functionality change intended, but the changes are extensive. Definitions of architecture types and subtypes are by no means exhaustive or perfectly defined, but a fair starting point. Suggestions for futher improvements are welcome. Reviewers: llvm-commits Differential Revision: http://reviews.llvm.org/D20988 llvm-svn: 271921
* [cpu-detection] Naming conventionAlina Sbirlea2016-06-031-28/+27
| | | | | | | | | | | | Summary: Follow-up to D20926 (committed as r271595, r271596). This patch is in preparation for a substantial refactoring of the code. No functionality changed. Differential Revision: http://reviews.llvm.org/D20970 llvm-svn: 271726
* 80-column fixup after last formatting change.Eric Christopher2016-06-021-4/+8
| | | | llvm-svn: 271598
* Fix a couple of misformatted comments spotted in post-commit review.Eric Christopher2016-06-021-8/+7
| | | | llvm-svn: 271596
* This patch is in preparation for a substantial refactoring of theEric Christopher2016-06-021-294/+304
| | | | | | | | | | | | code. To make the diffs easier to read, clang-format everything first. No functionality changed. Patch by Alina Sbirlea! http://reviews.llvm.org/D20926 llvm-svn: 271595
* Removing an unused variable introduced in r269911; NFC.Aaron Ballman2016-05-181-1/+0
| | | | llvm-svn: 269915
* Add new flag and intrinsic support for MWAITX and MONITORX instructionsAshutosh Nema2016-05-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper, RKSimon Subscribers: RKSimon, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19795 llvm-svn: 269911
* [Power9] Add support for -mcpu=pwr9 in the back endNemanja Ivanovic2016-05-091-0/+1
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D19683 Simply adds the bits for being able to specify -mcpu=pwr9 to the back end. llvm-svn: 268950
* [Support][X86] Add a few more Intel model numbers to getHostCPUName for ↵Craig Topper2016-04-271-0/+4
| | | | | | airmont and knl. llvm-svn: 267670
* [Support][X86] Change the case values in the Intel family 6 code to hex so ↵Craig Topper2016-04-271-68/+66
| | | | | | its easier to compare with Intel's docs. NFC llvm-svn: 267669
* [Support][X86] Add a couple more Broadwell CPU models numbers to getHostCPUName.Craig Topper2016-04-271-0/+2
| | | | llvm-svn: 267666
* Revert "Fix Clang-tidy modernize-deprecated-headers warnings in remaining ↵Duncan P. N. Exon Smith2016-04-051-13/+11
| | | | | | | | | | files; other minor fixes." This reverts commit r265454 since it broke the build. E.g.: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/22413/ llvm-svn: 265459
* Fix Clang-tidy modernize-deprecated-headers warnings in remaining files; ↵Eugene Zelenko2016-04-051-11/+13
| | | | | | | | | | | | other minor fixes. Some Include What You Use suggestions were used too. Use anonymous namespaces in source files. Differential revision: http://reviews.llvm.org/D18778 llvm-svn: 265454
* Fix LLVM's handling and detection of skylake and cannonlake CPUsSanjoy Das2016-02-211-0/+1
| | | | | | | | | | | | | | | | | Summary: - Rename `"skylake"` == SkylakeServerProc to `"skylake-avx512"` - Change `"skylake"` to denote SkylakeClientProc - Fix the detection of cpu family 6 and model 94 to be SkylakeClientProc instead of SkylakeServerProc - Remove the `"cnl"` for CannonLake Reviewers: craig.topper, delena Subscribers: zansari, echristo, qcolombet, RKSimon, spatel, DavidKreitzer, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17090 llvm-svn: 261482
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