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* [MC] Fix nested macro body parsingNirav Dave2018-07-181-1/+2
| | | | | | Add missing .rep case in nestlevel checking for macro body parsing. llvm-svn: 337398
* MC: Implement support for new .addrsig and .addrsig_sym directives.Peter Collingbourne2018-07-174-0/+87
| | | | | | | | | Part of the address-significance tables proposal: http://lists.llvm.org/pipermail/llvm-dev/2018-May/123514.html Differential Revision: https://reviews.llvm.org/D47744 llvm-svn: 337328
* [WebAssembly] Remove ELF file support.Sam Clegg2018-07-161-2/+1
| | | | | | | | | This support was partial and temporary. Now that we have wasm object file support its no longer needed. Differential Revision: https://reviews.llvm.org/D48744 llvm-svn: 337222
* [DWARF v5] Generate range list tables into the .debug_rnglists section. No ↵Wolfgang Pieb2018-07-121-0/+6
| | | | | | | | | | | | support for split DWARF and no use of DW_FORM_rnglistx with the DW_AT_ranges attribute. Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D49214 llvm-svn: 336927
* Use debug-prefix-map for AT_NAMEJonas Devlieghere2018-07-113-21/+20
| | | | | | | | | | | | | | | | | | AT_NAME was being emitted before the directory paths were remapped. This ensures that all paths are remapped before anything is emitted. An additional test case has been added. Note that this only works if the replacement string is an absolute path. If not, then AT_decl_file believes the new path is a relative path, and joins that path with the compilation directory. I do not know of a good way to resolve this. Patch by: Siddhartha Bagaria (starsid) Differential revision: https://reviews.llvm.org/D49169 llvm-svn: 336793
* [MC] Add interface to finish pending labels.Jonas Devlieghere2018-07-101-1/+1
| | | | | | | | | | | When manually finishing the object writer in dsymutil, it's possible that there are pending labels that haven't been resolved. This results in an assertion when the assembler tries to fixup a label that doesn't have an address yet. Differential revision: https://reviews.llvm.org/D49131 llvm-svn: 336688
* Support -fdebug-prefix-map in llvm-mc. This is useful to omit thePaul Robinson2018-07-103-4/+35
| | | | | | | | | | | debug compilation dir when compiling assembly files with -g. Part of PR38050. Patch by Siddhartha Bagaria! Differential Revision: https://reviews.llvm.org/D48988 llvm-svn: 336680
* [MC] Error on a .zerofill directive in a non-virtual sectionFrancis Visoiu Mistrih2018-07-027-14/+39
| | | | | | | | | | | | | | | On darwin, all virtual sections have zerofill type, and having a .zerofill directive in a non-virtual section is not allowed. Instead of asserting, show a nicer error. In order to use the equivalent of .zerofill in a non-virtual section, the usage of .zero of .space is required. This patch replaces the assert with an error. Differential Revision: https://reviews.llvm.org/D48517 llvm-svn: 336127
* Add an entry for rodata constant merge sections to the defaultEric Christopher2018-07-021-0/+3
| | | | | | | | | | section flags in the ELF assembler. This matches the defaults given in the rest of MC. Fixes PR37997 where we couldn't assemble our own assembly output without warnings. llvm-svn: 336072
* Add a warning if someone attempts to add extra section flags to sectionsEric Christopher2018-06-251-16/+33
| | | | | | with well defined semantics like .rodata. llvm-svn: 335558
* Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFCAlexander Richardson2018-06-251-2/+1
| | | | | | | | | | | | | | There are quite a few if statements that enumerate all these cases. It gets even worse in our fork of LLVM where we also have a Triple::cheri (which is mips64 + CHERI instructions) and we had to update all if statements that check for Triple::mips64 to also handle Triple::cheri. This patch helps to reduce our diff to upstream and should also make some checks more readable. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48548 llvm-svn: 335493
* [DWARFv5] Allow ".loc 0" to refer to the root file.Paul Robinson2018-06-222-4/+6
| | | | | | | | | DWARF v5 explicitly represents file #0 in the line table. Prior versions did not, so ".loc 0" is still an error in those cases. Differential Revision: https://reviews.llvm.org/D48452 llvm-svn: 335350
* Recommit r335333 "[MC] - Add .stack_size sections into groups and link them ↵George Rimar2018-06-221-0/+21
| | | | | | | | | | | | | | | | | | | | | | | with .text" With compilation fix. Original commit message: D39788 added a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. This change does following two things on top: 1) Imagine the case when there are -ffunction-sections flag given and there are text sections in COMDATs. The patch adds a '.stack-size' section into corresponding COMDAT group, so that linker will be able to eliminate them fast during resolving the COMDATs. 2) Patch sets a SHF_LINK_ORDER flag and links '.stack-size' with the corresponding .text. With that linker will be able to do -gc-sections on dead stack sizes sections. Differential revision: https://reviews.llvm.org/D46874 llvm-svn: 335336
* Revert r335332 "[MC] - Add .stack_size sections into groups and link them ↵George Rimar2018-06-221-21/+0
| | | | | | | | | | | | with .text" It broke bots. http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/12891 http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/9443 http://lab.llvm.org:8011/builders/lldb-x86_64-ubuntu-14.04-buildserver/builds/25551 llvm-svn: 335333
* [MC] - Add .stack_size sections into groups and link them with .textGeorge Rimar2018-06-221-0/+21
| | | | | | | | | | | | | | | | | D39788 added a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. This change does following two things on top: 1) Imagine the case when there are -ffunction-sections flag given and there are text sections in COMDATs. The patch adds a '.stack-size' section into corresponding COMDAT group, so that linker will be able to eliminate them fast during resolving the COMDATs. 2) Patch sets a SHF_LINK_ORDER flag and links '.stack-size' with the corresponding .text. With that linker will be able to do -gc-sections on dead stack sizes sections. Differential revision: https://reviews.llvm.org/D46874 llvm-svn: 335332
* [mingw] Fix GCC ABI compatibility for comdat thingsReid Kleckner2018-06-212-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC and the binutils COFF linker do comdats differently from MSVC. If we want to be ABI compatible, we have to do what they do, which is to emit unique section names like ".text$_Z3foov" instead of short section names like ".text". Otherwise, the binutils linker gets confused and reports multiple definition errors when two object files from GCC and Clang containing the same inline function are linked together. The best description of the issue is probably at https://github.com/Alexpux/MINGW-packages/issues/1677, we don't seem to have a good one in our tracker. I fixed up the .pdata and .xdata sections needed everywhere other than 32-bit x86. GCC doesn't use associative comdats for those, it appears to rely on the section name. Reviewers: smeenai, compnerd, mstorsjo, martell, mati865 Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D48402 llvm-svn: 335286
* [DWARF] Warn on and ignore ".file 0" for DWARF v4 and earlier.Paul Robinson2018-06-211-2/+4
| | | | | | | This had been messing with the directory table for prior versions, and also could induce a crash when generating asm output. llvm-svn: 335254
* Remove FIXME comment about WIP.Eric Christopher2018-06-211-1/+0
| | | | | | | This is the only line other than the function signature remaining of the original patch. llvm-svn: 335208
* [DWARF] Don't keep a ref to possibly stack allocated data.Paul Robinson2018-06-201-2/+2
| | | | llvm-svn: 335146
* Remove a redundant initialization. NFCPaul Robinson2018-06-201-1/+1
| | | | llvm-svn: 335143
* [llvm-mca][X86] Teach how to identify register writes that implicitly clear ↵Andrea Di Biagio2018-06-201-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the upper portion of a super-register. This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
* Fix typoed cast to avoid assertion in MCFragment::dump.Nirav Dave2018-06-181-1/+1
| | | | llvm-svn: 334959
* [PowerPC] Add support for high and higha symbol modifiers on tls modifers.Sean Fertile2018-06-152-0/+12
| | | | | | | | | | Enables using the high and high-adjusted symbol modifiers on thread local storage modifers in powerpc assembly. Needed to be able to support 64 bit thread-pointer and dynamic-thread-pointer access sequences. Differential Revision: https://reviews.llvm.org/D47754 llvm-svn: 334856
* [PPC64] Support "symbol@high" and "symbol@higha" symbol modifers.Sean Fertile2018-06-151-0/+4
| | | | | | | | | | Add support for the "@high" and "@higha" symbol modifiers in powerpc64 assembly. The modifiers represent accessing the segment consiting of bits 16-31 of a 64-bit address/offset. Differential Revision: https://reviews.llvm.org/D47729 llvm-svn: 334855
* [MC] Move bundling and MCSubtargetInfo to MCEncodedFragment [NFC]Peter Smith2018-06-153-21/+25
| | | | | | | | | | | | | | Instruction bundling is only supported on descendants of the MCEncodedFragment type. By moving the bundling functionality and MCSubtargetInfo to this class it makes it easier to set and extract the MCSubtargetInfo when it is necessary. This is a refactoring change that will make it easier to pass the MCSubtargetInfo through to writeNops when nop padding is required. Differential Revision: https://reviews.llvm.org/D45959 llvm-svn: 334814
* Revert "[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer."Sam Clegg2018-06-143-30/+24
| | | | | | | | | This reverts rL331412. We didn't up using fragment atoms in the wasm object writer after all. Differential Revision: https://reviews.llvm.org/D48173 llvm-svn: 334734
* [MC] Move MCAssembler::dump into the correct cpp file. NFCSam Clegg2018-06-142-22/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D46556 llvm-svn: 334713
* [DWARFv5] Tolerate files not all having an MD5 checksum.Paul Robinson2018-06-143-15/+27
| | | | | | | | | | | | | | | | | | In some cases, for example when compiling a preprocessed file, the front-end is not able to provide an MD5 checksum for all files. When that happens, omit the MD5 checksums from the final DWARF, because DWARF doesn't have a way to indicate that some but not all files have a checksum. When assembling a .s file, and some but not all .file directives provide an MD5 checksum, issue a warning and don't emit MD5 into the DWARF. Fixes PR37623. Differential Revision: https://reviews.llvm.org/D48135 llvm-svn: 334710
* [DWARFv5] llvm-mc -dwarf-version does not imply -g.Paul Robinson2018-06-121-7/+14
| | | | | | | | | | | | | Don't provide the assembler source as the "root file" unless the user asked to have debug info for the assembler source (with -g). If the source doesn't provide an explicit ".file 0" then (a) use the compilation directory as directory #0, and (b) use the file #1 info for file #0 also. Differential Revision: https://reviews.llvm.org/D48055 llvm-svn: 334512
* AMDGPU: Add 64-bit relative variant kindKonstantin Zhuravlyov2018-06-111-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D47601 llvm-svn: 334443
* [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixupPeter Smith2018-06-068-26/+64
| | | | | | | | | | | | | | | | | | On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-7/+19
| | | | | | | | | | | | | This is a fix for the problem arising in D47374 (PR37678): https://bugs.llvm.org/show_bug.cgi?id=37678 We may not have throughput info because it's not specified in the model or it's not available with variant scheduling, so assume that those instructions can execute/complete at max-issue-width. Differential Revision: https://reviews.llvm.org/D47723 llvm-svn: 334055
* [MC][X86] Allow assembler variable assignment to register name.Nirav Dave2018-06-053-22/+35
| | | | | | | | | | | | | | | | | | | Summary: Allow extended parsing of variable assembler assignment syntax and modify X86 to permit VAR = register assignment. As we emit these as .set directives when possible, we inline such expressions in output assembly. Fixes PR37425. Reviewers: rnk, void, echristo Reviewed By: rnk Subscribers: nickdesaulniers, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D47545 llvm-svn: 334022
* [MC] Add assembler support for .cg_profile.Michael J. Spencer2018-06-026-0/+123
| | | | | | | | | | | | | | | Object FIle Representation At codegen time this is emitted into the ELF file a pair of symbol indices and a weight. In assembly it looks like: .cg_profile a, b, 32 .cg_profile freq, a, 11 .cg_profile freq, b, 20 When writing an ELF file these are put into a SHT_LLVM_CALL_GRAPH_PROFILE (0x6fff4c02) section as (uint32_t, uint32_t, uint64_t) tuples as (from symbol index, to symbol index, weight). Differential Revision: https://reviews.llvm.org/D44965 llvm-svn: 333823
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-311-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [WebAssembly] MC: Add compile-twice test and fix corresponding bugSam Clegg2018-05-302-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D47398 llvm-svn: 333494
* [RISCV] Add symbol diff relocation support for RISC-VAlex Bradbury2018-05-233-4/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
* MC: Remove dead code. NFCI.Peter Collingbourne2018-05-221-11/+0
| | | | | | | This code appears to have been copied from the mach-o streamer. It has no effect in ELF because indirect symbols are specific to mach-o. llvm-svn: 332926
* MC: Introduce an ELF dwo object writer and teach llvm-mc about it.Peter Collingbourne2018-05-212-15/+103
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47051 llvm-svn: 332875
* MC: Extract a derived class from ELFObjectWriter. NFCI.Peter Collingbourne2018-05-211-13/+19
| | | | | | | | | | This class will be used to create regular, non-split ELF files. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47049 llvm-svn: 332870
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-211-0/+26
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Extract ELFObjectWriter's ELF writing functionality into an ELFWriter ↵Peter Collingbourne2018-05-211-350/+368
| | | | | | | | | | | class. NFCI. The idea is that we will be able to use this class to create multiple files. Differential Revision: https://reviews.llvm.org/D47048 llvm-svn: 332867
* MC: Remove stream and output functions from MCObjectWriter. NFCI.Peter Collingbourne2018-05-213-5/+3
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47043 llvm-svn: 332864
* MC: Have the object writers return the number of bytes written. NFCI.Peter Collingbourne2018-05-215-17/+27
| | | | | | | | | | This removes the last external use of the stream. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47042 llvm-svn: 332863
* MC: Change object writers to use endian::Writer. NFCI.Peter Collingbourne2018-05-215-355/+364
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47040 llvm-svn: 332861
* MC: Change MCAssembler::writeSectionData and writeFragmentPadding to take a ↵Peter Collingbourne2018-05-216-65/+50
| | | | | | | | | | | | | | raw_ostream. NFCI. Also clean up a couple of hacks where we were writing the section contents to another stream by setting the object writer's stream, writing and setting it back. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47038 llvm-svn: 332858
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-212-8/+6
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-183-13/+7
| | | | | | | | | | | | Provide some free functions to reduce verbosity of endian-writing a single value, and replace the endianness template parameter with a field. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47032 llvm-svn: 332757
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-185-16/+20
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* [MC] Relax .fill size requirementsNirav Dave2018-05-184-33/+60
| | | | | | | | | | | | | | | Avoid requirement that number of values must be known at assembler time. Fixes PR33586. Reviewers: rnk, peter.smith, echristo, jyknight Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46703 llvm-svn: 332741
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