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* [DWARF] Fix a few corner cases in expression emissionKeno Fischer2015-06-093-9/+33
| | | | | | | | | | | | | | | | | | | Summary: I noticed an object file with `DW_OP_reg4 DW_OP_breg4 0` as a DWARF expression, which I traced to a missing break (and `++I`) in this code snippet. While I was at it, I also added support for a few other corner cases along the same lines that I could think of. Test Plan: Hand-crafted test case to exercises these cases is included. Reviewers: echristo, dblaikie, aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10302 llvm-svn: 239380
* Implement computeKnownBits for min/max nodesMatt Arsenault2015-06-091-1/+22
| | | | llvm-svn: 239378
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-3/+4
| | | | llvm-svn: 239370
* [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFCKeno Fischer2015-06-081-7/+8
| | | | | | | | | | | | | | | | | | Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
* [ARM] Pass a callback to FunctionPass constructors to enable skipping executionAkira Hatanaka2015-06-082-2/+24
| | | | | | | | | | | | | | | | on a per-function basis. Previously some of the passes were conditionally added to ARM's pass pipeline based on the target machine's subtarget. This patch makes changes to add those passes unconditionally and execute them conditonally based on the predicate functor passed to the pass constructors. This enables running different sets of passes for different functions in the module. rdar://problem/20542263 Differential Revision: http://reviews.llvm.org/D8717 llvm-svn: 239325
* Fix assertion failure in global-merge with unused ConstantExprOliver Stannard2015-06-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The global-merge pass was crashing because it assumes that all ConstantExprs (reached via the global variables that they use) have at least one user. I haven't worked out a way to test this, as an unused ConstantExpr cannot be represented by serialised IR, and global-merge can only be run in llc, which does not run any passes which can make a ConstantExpr dead. This (reduced to the point of silliness) C code triggers this bug when compiled for arm-none-eabi at -O1: static a = 7; static volatile b[10] = {&a}; c; main() { c = 0; for (; c < 10;) printf(b[c]); } Differential Revision: http://reviews.llvm.org/D10314 llvm-svn: 239308
* [DAGCombiner] Added CTLZ vector constant folding support.Simon Pilgrim2015-06-082-2/+4
| | | | llvm-svn: 239305
* [DAGCombiner] Added CTTZ vector constant folding support.Simon Pilgrim2015-06-082-2/+4
| | | | llvm-svn: 239293
* [DAGCombiner] Added CTPOP vector constant folding support.Simon Pilgrim2015-06-072-2/+3
| | | | | | Added tests to the existing SSE/AVX test files. llvm-svn: 239252
* Move the code in TargetPassConfig::addPass that inserts machine printer pass toAkira Hatanaka2015-06-051-16/+18
| | | | | | | | | | | the overloaded version of addPass which takes Pass*. This change enables inserting the machine printer pass when the overloaded version of addPass that takes Pass* is called to add a pass, instead of the one which takes AnalysisID. I need this to prevent make-check tests from failing when I commit another patch later. llvm-svn: 239192
* DAGCombiner: don't duplicate (fmul x, c) in visitFNEG if fneg is freeFiona Glaser2015-06-051-1/+2
| | | | | | | | | | For targets with a free fneg, this fold is always a net loss if it ends up duplicating the multiply, so definitely avoid it. This might be true for some targets without a free fneg too, but I'll leave that for future investigation. llvm-svn: 239167
* Simplify code; NFC.Andrea Di Biagio2015-06-051-7/+7
| | | | | | | | Also, moved test cases from CodeGen/X86/fold-buildvector-bug.ll into CodeGen/X86/buildvec-insertvec.ll and regenerated CHECK lines using update_llc_test_checks.py. llvm-svn: 239142
* Statepoint: Fix handling of Far Immediate callsSwaroop Sridhar2015-06-041-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | gc.statepoint intrinsics with a far immediate call target were lowered incorrectly as pc-rel32 calls. This change fixes the problem, and generates an indirect call via a scratch register. For example: Intrinsic: %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* inttoptr (i64 140727162896504 to void ()*), i32 0, i32 0, i32 0, i32 0) Old Incorrect Lowering: callq 140727162896504 New Correct Lowering: movabsq $140727162896504, %rax callq *%rax In lowerCallFromStatepoint(), the callee-target was modified and represented as a "TargetConstant" node, rather than a "Constant" node. Undoing this modification enabled LowerCall() to generate the correct CALL instruction. llvm-svn: 239114
* [SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MINBenjamin Kramer2015-06-041-9/+5
| | | | | | | | | | | The big/small ordering here is based on signed values so SmallValue will be INT_MIN and BigValue 0. This shouldn't be a problem but the code assumed that BigValue always had more bits set than SmallValue. We used to just miss the transformation, but a recent refactoring of mine turned this into an assertion failure. llvm-svn: 239105
* Erase constant dbgloc on reuse in PHI nodeSergey Dmitrouk2015-06-041-1/+10
| | | | | | | | | | | | | | | | | | | | Basic block selection involves checking successor BBs for PHI nodes that depend on the current BB. In case such BBs are found, the value being selected is a constant and such constant already exists in current BB, it's value is reused. This might lead to wrong locations in some situations, especially if same constant value ends up being materialized twice in two different ways, which discards that sharing and leaves us with wrong debug location in the successor BB. In code this involves the following sequence of calls: SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks -> SelectionDAGBuilder::CopyValueToVirtualRegister -> SelectionDAGBuilder::getNonRegisterValue llvm-svn: 239089
* [GlobalMerge] Take into account minsize on Global users' parents.Ahmed Bougacha2015-06-041-4/+18
| | | | | | | | | | Now that we can look at users, we can trivially do this: when we would have otherwise disabled GlobalMerge (currently -O<3), we can just run it for minsize functions, as it's usually a codesize win. Differential Revision: http://reviews.llvm.org/D10054 llvm-svn: 239087
* [DAGCombiner] Fix wrong folding of a build_vector into a blend with zero.Andrea Di Biagio2015-06-041-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Method 'visitBUILD_VECTOR' in the DAGCombiner knows how to combine a build_vector of a bunch of extract_vector_elt nodes and constant zero nodes into a shuffle blend with a zero vector. However, method 'visitBUILD_VECTOR' forgot that a floating point build_vector may contain negative zero as well as positive zero. Example: define <2 x double> @example(<2 x double> %A) { entry: %0 = extractelement <2 x double> %A, i32 0 %1 = insertelement <2 x double> undef, double %0, i32 0 %2 = insertelement <2 x double> %1, double -0.0, i32 1 ret <2 x double> %2 } Before this patch, llc (with -mattr=+sse4.1) wrongly generated movq %xmm0, %xmm0 # xmm0 = xmm0[0],zero So, the sign bit of the negative zero was effectively lost. This patch fixes the problem by adding explicit checks for positive zero. With this patch, llc produces the following code for the example above: movhpd .LCPI0_0(%rip), %xmm0 where .LCPI0_0 referes to a 'double -0'. llvm-svn: 239070
* [SDag switch lowering] Simplify code a bit. No functional change intended.Benjamin Kramer2015-06-041-10/+9
| | | | llvm-svn: 239056
* CodeGenPrepare: Provide address space to isLegalAddressingModeMatt Arsenault2015-06-041-26/+40
| | | | | | Use -1 as the address space if it can't be determined. llvm-svn: 239052
* Pass address space to isLegalAddressingMode in DAGCombinerMatt Arsenault2015-06-041-1/+5
| | | | | | | No test because I don't know of a target that makes use of address spaces and indexed load / store. llvm-svn: 239051
* Switch lowering: fix assert in buildBitTests (PR23738)Hans Wennborg2015-06-041-1/+2
| | | | | | | | When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated to the size of the left-hand side. In the case of this PR, the left-hand side was i4, so BitWidth=64 got truncated to 0 and the assert failed. llvm-svn: 239048
* Don't create a MIN/MAX node if the underlying compare has more than one use.James Molloy2015-06-041-1/+5
| | | | | | | | | If the compare in a select pattern has another use then it can't be removed, so we'd just be creating repeated code if we created a min/max node. Spotted by Matt Arsenault! llvm-svn: 239037
* [SelectionDAG] Fix PR23603.Sanjoy Das2015-06-021-1/+11
| | | | | | | | | | | | | | | | | | | | | Summary: LLVM's MI level notion of invariant_load is different from LLVM's IR level notion of invariant_load with respect to dereferenceability. The IR notion of invariant_load only guarantees that all *non-faulting* invariant loads result in the same value. The MI notion of invariant load guarantees that the load can be legally moved to any location within its containing function. The MI notion of invariant_load is stronger than the IR notion of invariant_load -- an MI invariant_load is an IR invariant_load + a guarantee that the location being loaded from is dereferenceable throughout the function's lifetime. Reviewers: hfinkel, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10075 llvm-svn: 238881
* Create a MCSymbolELF.Rafael Espindola2015-06-022-6/+8
| | | | | | | | | This create a MCSymbolELF class and moves SymbolSize since only ELF needs a size expression. This reduces the size of MCSymbol from 56 to 48 bytes. llvm-svn: 238801
* LiveRangeEdit: Fix liveranges not shrinking on subrange kill.Matthias Braun2015-06-011-3/+18
| | | | | | | | | | | | | | If a dead instruction we may not only have a last-use in the main live range but also in a subregister range if subregisters are tracked. We need to partially rebuild live ranges in both cases. The testcase only broke when subregister liveness was enabled. I commited it in the current form because there is currently no flag to enable/disable subregister liveness. This fixes PR23720. llvm-svn: 238785
* Disable MachineSink on convergent operations, similar to how IR Sink isOwen Anderson2015-06-011-0/+4
| | | | | | | restricted. No test because no in-tree target currently has convergent MachineInstr's. llvm-svn: 238763
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-1/+2
| | | | | | | | | | This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. llvm-svn: 238723
* [sdag] Add the helper I most want to the DAG -- building a bitcastChandler Carruth2015-05-301-0/+7
| | | | | | | | around a value using its existing SDLoc. Start using this in just one function to save omg lines of code. llvm-svn: 238638
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-308-64/+64
| | | | llvm-svn: 238634
* SelectionDAG: fix logic for promoting shift typesFiona Glaser2015-05-291-15/+21
| | | | | | | | | | | r238503 fixed the problem of too-small shift types by promoting them during legalization, but the correct solution is to promote only the operands that actually demand promotion. This fixes a crash on an out-of-tree target caused by trying to promote an operand that can't be promoted. llvm-svn: 238632
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-293-6/+6
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* MachineCopyPropagation: Remove the copies instead of using KILL instructions.Matthias Braun2015-05-292-22/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some history here see the commit messages of r199797 and r169060. The original intent was to fix cases like: %EAX<def> = COPY %ECX<kill>, %RAX<imp-def> %RCX<def> = COPY %RAX<kill> where simply removing the copies would have RCX undefined as in terms of machine operands only the ECX part of it is defined. The machine verifier would complain about this so 169060 changed such COPY instructions into KILL instructions so some super-register imp-defs would be preserved. In r199797 it was finally decided to always do this regardless of super-register defs. But this is wrong, consider: R1 = COPY R0 ... R0 = COPY R1 getting changed to: R1 = KILL R0 ... R0 = KILL R1 It now looks like R0 dies at the first KILL and won't be alive until the second KILL, while in reality R0 is alive and must not change in this part of the program. As this only happens after register allocation there is not much code still performing liveness queries so the issue was not noticed. In fact I didn't manage to create a testcase for this, without unrelated changes I am working on at the moment. The fix is simple: As of r223896 the MachineVerifier allows reads from partially defined registers, so the whole transforming COPY->KILL thing is not necessary anymore. This patch also changes a similar (but more benign case as the def and src are the same register) case in the VirtRegRewriter. Differential Revision: http://reviews.llvm.org/D10117 llvm-svn: 238588
* MIR Serialization: use correct line and column numbers for LLVM IR errors.Alex Lorenz2015-05-291-1/+40
| | | | | | | | | | | | | This commit translates the line and column numbers for LLVM IR errors from the numbers in the YAML block scalar to the numbers in the MIR file so that the MIRParser users can report LLVM IR errors with the correct line and column numbers. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10108 llvm-svn: 238576
* [WinEH] Emit EH tables for __CxxFrameHandler3 on 32-bit x86Reid Kleckner2015-05-294-137/+186
| | | | | | | | | | | | | Small (really small!) C++ exception handling examples work on 32-bit x86 now. This change disables the use of .seh_* directives in WinException when CFI is not in use. It also uses absolute symbol references in the tables instead of imagerel32 relocations. Also fixes a cache invalidation bug in MMI personality classification. llvm-svn: 238575
* This should have been a referenceMatthias Braun2015-05-291-1/+1
| | | | llvm-svn: 238540
* CodeGen: Use mop_iterator instead of MIOperands/ConstMIOperandsMatthias Braun2015-05-298-74/+80
| | | | | | | | | | | | | | | | | | | | | | | | MIOperands/ConstMIOperands are classes iterating over the MachineOperand of a MachineInstr, however MachineInstr::mop_iterator does the same thing. I assume these two iterators exist to have a uniform interface to iterate over the operands of a machine instruction bundle and a single machine instruction. However in practice I find it more confusing to have 2 different iterator classes, so this patch transforms (nearly all) the code to use mop_iterators. The only exception being MIOperands::anlayzePhysReg() and MIOperands::analyzeVirtReg() still needing an equivalent, I leave that as an exercise for the next patch. Differential Revision: http://reviews.llvm.org/D9932 This version is slightly modified from the proposed revision in that it introduces MachineInstr::getOperandNo to avoid the extra counting variable in the few loops that previously used MIOperands::getOperandNo. llvm-svn: 238539
* MachineFrameInfo: Simplify pristine register calculation.Matthias Braun2015-05-285-50/+9
| | | | | | | | | | | | | | | | | | | | | | | | | About pristine regsiters: Pristine registers "hold a value that is useless to the current function, but that must be preserved - they are callee saved registers that have not been saved." This concept saves compile time as it frees the prologue/epilogue inserter from adding every such register to every basic blocks live-in list. However the current code in getPristineRegs is formulated in a complicated way: Inside the function prologue and epilogue all callee saves are considered pristine, while in the rest of the code only the non-saved ones are considered pristine. This requires logic to differentiate between prologue/epilogue and the rest and in the presence of shrink-wrapping this even becomes complicated/expensive. It's also unnecessary because the prologue epilogue inserters already mark callee-save registers that are saved/restores properly in the respective blocks in the prologue/epilogue (see updateLiveness() in PrologueEpilogueInserter.cpp). So only declaring non-saved/restored callee saved registers as pristine just works. Differential Revision: http://reviews.llvm.org/D10101 llvm-svn: 238524
* Rename Win64Exception.(cpp|h) to WinException.(cpp|h)Reid Kleckner2015-05-284-18/+18
| | | | | | | This is in preparation for reusing this for 32-bit x86 EH table emission. Also updates the type name for consistency. NFC llvm-svn: 238521
* MIR Serialization: print and parse machine function names.Alex Lorenz2015-05-282-15/+81
| | | | | | | | | | | | | | | | | | This commit introduces a serializable structure called 'llvm::yaml::MachineFunction' that stores the machine function's name. This structure will mirror the machine function's state in the future. This commit prints machine functions as YAML documents containing a YAML mapping that stores the state of a machine function. This commit also parses the YAML documents that contain the machine functions. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D9841 llvm-svn: 238519
* [MachineCopyPropagation] Fix a bug with undef handling when the value is ↵Quentin Colombet2015-05-281-5/+9
| | | | | | | | actualy alive. Test case will follow. llvm-svn: 238518
* [WinEH] Start inserting state number stores for C++ EHReid Kleckner2015-05-282-371/+377
| | | | | | | | | | | | This moves all the state numbering code for C++ EH to WinEHPrepare so that we can call it from the X86 state numbering IR pass that runs before isel. Now we just call the same state numbering machinery and insert a bunch of stores. It also populates MachineModuleInfo with information about the current function. llvm-svn: 238514
* [SelectionDAG] Scalar shift amounts may require legalizationDavid Majnemer2015-05-281-3/+6
| | | | | | | | | The shift amount may be too small to cope with promoted left hand side, make sure to promote it as well. This fixes PR23664. llvm-svn: 238503
* AsmPrinter: Stop exposing underlying DIE children list, NFCDuncan P. N. Exon Smith2015-05-284-8/+5
| | | | | | | Update `DIE` API to hide the implementation of `DIE::Children` so we can swap it out. llvm-svn: 238468
* AsmPrinter: Rename begin_values() => values_begin(), NFCDuncan P. N. Exon Smith2015-05-281-2/+2
| | | | llvm-svn: 238456
* [AsmPrinter] Destroy allocated DIEAbbrevs on teardown.Benjamin Kramer2015-05-281-1/+4
| | | | | | | | | | DIEAbbrev contains a SmallVector that can leak for overly large abbrevs. They used to be owned by the DIE, but after the recent refactoring DWARFFile allocates its own abbrevs. Leak found by asan. llvm-svn: 238418
* AsmPrinter: Avoid a warning in NDEBUG, NFCDuncan P. N. Exon Smith2015-05-271-0/+1
| | | | | | | Should fix the -Werror release build: http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/11113 llvm-svn: 238375
* AsmPrinter: Return added DIE from DIE::addChild()Duncan P. N. Exon Smith2015-05-271-2/+1
| | | | | | | | | Change `DIE::addChild()` to return a reference to the just-added node, and update consumers to use it directly. An upcoming commit will abstract away (and eventually change) the underlying storage of `DIE::Children`. llvm-svn: 238372
* RegisterPressure: fix debug prints in case of physical registersFiona Glaser2015-05-271-2/+2
| | | | llvm-svn: 238371
* AsmPrinter: Stop exposing underlying DIEValue list, NFCDuncan P. N. Exon Smith2015-05-276-37/+26
| | | | | | | Change the `DIE` API to hide the implementation of the list of `DIEValue`s. llvm-svn: 238369
* AsmPrinter: Remove DIEHash::AttrEntry, NFCDuncan P. N. Exon Smith2015-05-272-62/+53
| | | | | | Remove "the most boring struct ever" (thanks to review by Eric). llvm-svn: 238366
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