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* Strip trailing whitespace. NFCI.Simon Pilgrim2017-05-111-1/+1
| | | | llvm-svn: 302784
* Remove spurious cast of nullptr. NFC.Serge Guelton2017-05-111-1/+1
| | | | | | Conversion rules allow automatic casting of nullptr to any pointer type. llvm-svn: 302780
* Revert "[SDAG] Relax conditions under stores of loaded values can be merged"David L. Jones2017-05-101-22/+10
| | | | | | | | | | | | | | | | | | | | | This reverts r302712. The change fails with ASAN enabled: ERROR: AddressSanitizer: use-after-poison on address ... at ... READ of size 2 at ... thread T0 #0 ... in llvm::SDNode::getNumValues() const <snip>/include/llvm/CodeGen/SelectionDAGNodes.h:855:42 #1 ... in llvm::SDNode::hasAnyUseOfValue(unsigned int) const <snip>/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7270:3 #2 ... in llvm::SDValue::use_empty() const <snip> include/llvm/CodeGen/SelectionDAGNodes.h:1042:17 #3 ... in (anonymous namespace)::DAGCombiner::MergeConsecutiveStores(llvm::StoreSDNode*) <snip>/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12944:7 Reviewers: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33081 llvm-svn: 302746
* [PHIElimination] Use the same name for DEBUG_TYPE and pass name.Davide Italiano2017-05-101-1/+1
| | | | | | In an attempt to reduce the confusion. llvm-svn: 302742
* [SDAG] Relax conditions under stores of loaded values can be mergedNirav Dave2017-05-101-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
* Small refactoring in DAGCombine. NFCAmaury Sechet2017-05-101-3/+3
| | | | llvm-svn: 302699
* [DAGCombiner] Dropped explicit (sra 0, x) -> 0 and (sra -1, x) -> 0 folds.Simon Pilgrim2017-05-101-6/+2
| | | | | | These are both handled (and tested) by the earlier ComputeNumSignBits == EltSizeInBits fold. llvm-svn: 302651
* [IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen2017-05-101-1/+2
| | | | | | | | | | | | | | | | | Summary: When trying to figure out if MBB could fallthrough to ToMBB (possibly by falling through a bunch of other MBBs) we didn't actually check if there was fallthrough between the last two blocks in the chain. Reviewers: kparzysz, iteratee, MatzeB Reviewed By: kparzysz, iteratee Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32996 llvm-svn: 302650
* [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0Simon Pilgrim2017-05-101-2/+2
| | | | llvm-svn: 302641
* Add a late IR expansion pass for the experimental reduction intrinsics.Amara Emerson2017-05-103-0/+171
| | | | | | | | | This pass uses a new target hook to decide whether or not to expand a particular intrinsic to the shuffevector sequence. Differential Revision: https://reviews.llvm.org/D32245 llvm-svn: 302631
* [UnreachableBlockElim] Check return value of constrainRegClass().Mikael Holmen2017-05-101-3/+4
| | | | | | | | | | | | | | | | | | | Summary: MachineRegisterInfo::constrainRegClass() can fail if two register classes don't have a common subclass or if the register class doesn't contain enough registers. Check the return value before trying to remove Phi nodes, and if we can't constrain, we output a COPY instead of simply replacing registers. Reviewers: kparzysz, david2050, wmi Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32999 llvm-svn: 302622
* [CodeGen] Don't require AA in TwoAddress at -O0.Ahmed Bougacha2017-05-101-2/+5
| | | | | | | | | | | | | This is a follow-up to r302611, which moved an -O0 computation of DT from SDAGISel to TwoAddress. Don't use it here either, and avoid computing it completely. The only use was forwarding the analysis as an optional argument to utility functions. Differential Revision: https://reviews.llvm.org/D32766 llvm-svn: 302612
* [CodeGen] Don't require AA in SDAGISel at -O0.Ahmed Bougacha2017-05-104-27/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Before r247167, the pass manager builder controlled which AA implementations were used, exporting them all in the AliasAnalysis analysis group. Now, AAResultsWrapperPass always uses BasicAA, but still uses other AA implementations if made available in the pass pipeline. But regardless, SDAGISel is required at O0, and really doesn't need to be doing fancy optimizations based on useful AA results. Don't require AA at CodeGenOpt::None, and only use it otherwise. This does have a functional impact (and one testcase is pessimized because we can't reuse a load). But I think that's desirable no matter what. Note that this alone doesn't result in less DT computations: TwoAddress was previously able to reuse the DT we computed for SDAG. That will be fixed separately. Differential Revision: https://reviews.llvm.org/D32766 llvm-svn: 302611
* [CodeGen] Compute DT/LI lazily in SafeStackLegacyPass. NFC.Ahmed Bougacha2017-05-101-2/+15
| | | | | | | | | | | | | We currently require SCEV, which requires DT/LI. Those are expensive to compute, but the pass only runs for functions that have the safestack attribute. Compute DT/LI to build SCEV lazily, only when the pass is actually going to transform the function. Differential Revision: https://reviews.llvm.org/D31302 llvm-svn: 302610
* [CodeGen] Split SafeStack into a LegacyPass and a utility. NFC.Ahmed Bougacha2017-05-102-72/+89
| | | | | | | | | This lets the pass focus on gathering the required analyzes, and the utility class focus on the transformation. Differential Revision: https://reviews.llvm.org/D31303 llvm-svn: 302609
* DAGCombine: Combine shuffles of splat-shufflesZvi Rackover2017-05-091-0/+54
| | | | | | | | | | | | | | Summary: Reapply r299047, but this time handle correctly splat-masks with undef elements. Reviewers: spatel, RKSimon, eli.friedman, andreadb Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31961 llvm-svn: 302583
* [codeview] Check for a DIExpression offset for local variablesReid Kleckner2017-05-091-1/+9
| | | | | | | | Fixes inalloca parameters, which previously all pointed to the same offset. Extend the test to use llvm-readobj so that we can test the offset in a readable way. llvm-svn: 302578
* Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton2017-05-091-2/+2
| | | | | | | | | Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential Revision: https://reviews.llvm.org/D32541 llvm-svn: 302571
* [RegScavenger] Rangify a loop, NFCKrzysztof Parzyszek2017-05-091-4/+3
| | | | llvm-svn: 302554
* Re-land "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-094-41/+68
| | | | | | This re-lands r302483. It was not the cause of PR32977. llvm-svn: 302544
* Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-091-14/+0
| | | | | | This re-lands commit r302461. It was not the cause of PR32977. llvm-svn: 302543
* [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction ↵Tim Shen2017-05-091-22/+9
| | | | | | | | | | | | | | | | | instead. NFC. Now both emitLeadingFence and emitTrailingFence take the instruction itself, instead of taking IsLoad/IsStore pairs. Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used for determining those two booleans. The instruction argument is also useful for later D32763, in emitTrailingFence. For emitLeadingFence, it seems to have cleaner interface with the proposed change. Differential Revision: https://reviews.llvm.org/D32762 llvm-svn: 302539
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-094-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* Introduce experimental generic intrinsics for horizontal vector reductions.Amara Emerson2017-05-096-1/+163
| | | | | | | | | | | | | | - This change allows targets to opt-in to using them instead of the log2 shufflevector algorithm. - The SLP and Loop vectorizers have the common code to do shuffle reductions factored out into LoopUtils, and now have a unified interface for generating reductions regardless of the preference of the target. LoopUtils now uses TTI to determine what kind of reductions the target wants to handle. - For CodeGen, basic legalization support is added. Differential Revision: https://reviews.llvm.org/D30086 llvm-svn: 302514
* Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-091-0/+14
| | | | | | | | | | This reverts commit r302461. It appears to be causing failures compiling gtest with debug info on the Linux sanitizer bot. I was unable to reproduce the failure locally, however. llvm-svn: 302504
* Fix code section prefix for proper layoutTeresa Johnson2017-05-091-1/+1
| | | | | | | | | | | | | | | | | | Summary: r284533 added hot and cold section prefixes based on profile information, to enable grouping of hot/cold functions at link time. However, it used "cold" as the prefix for cold sections, but gold only recognizes "unlikely" (which is used by gcc for cold sections). Therefore, cold sections were not properly being grouped. Switch to using "unlikely" Reviewers: danielcdh, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32983 llvm-svn: 302502
* Revert "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-094-68/+41
| | | | | | This reverts r302483 and it's follow up fix. llvm-svn: 302493
* Ignore !associated metadata with null argument.Evgeniy Stepanov2017-05-081-1/+5
| | | | | | | Fixes PR32577 (comment 10). Such metadata may legitimately appear in LTO. llvm-svn: 302485
* Use the frame index side table for byval and inalloca argumentsReid Kleckner2017-05-084-41/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For inalloca functions, this is a very common code pattern: %argpack = type <{ i32, i32, i32 }> define void @f(%argpack* inalloca %args) { entry: %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0 %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1 %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2 tail call void @llvm.dbg.declare(metadata i32* %a, ... "a") tail call void @llvm.dbg.declare(metadata i32* %c, ... "b") tail call void @llvm.dbg.declare(metadata i32* %b, ... "c") Even though these GEPs can be simplified to a constant offset from EBP or RSP, we don't do that at -O0, and each GEP is computed into a register. Registers used to compute argument addresses are typically spilled and clobbered very quickly after the initial computation, so live debug variable tracking loses information very quickly if we use DBG_VALUE instructions. This change moves processing of dbg.declare between argument lowering and basic block isel, so that we can ask if an argument has a frame index or not. If the argument lives in a register as is the case for byval arguments on some targets, then we don't put it in the side table and during ISel we emit DBG_VALUE instructions. Reviewers: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32980 llvm-svn: 302483
* Don't add DBG_VALUE instructions for static allocas in dbg.declareReid Kleckner2017-05-081-14/+0
| | | | | | | | | | | | | | | | | | | | | | | Summary: An llvm.dbg.declare of a static alloca is always added to the MachineFunction dbg variable map, so these values are entirely redundant. They survive all the way through codegen to be ignored by DWARF emission. Effectively revert r113967 Two bugpoint-reduced test cases from 2012 broke as a result of this change. Despite my best efforts, I haven't been able to rewrite the test case using dbg.value. I'm not too concerned about the lost coverage because these were reduced from the test-suite, which we still run. Reviewers: aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32920 llvm-svn: 302461
* [XRay] Custom event logging intrinsicDean Michael Berris2017-05-082-0/+52
| | | | | | | | | | | | | | | | | | | | This patch introduces an LLVM intrinsic and a target opcode for custom event logging in XRay. Initially, its use case will be to allow users of XRay to log some type of string ("poor man's printf"). The target opcode compiles to a noop sled large enough to enable calling through to a runtime-determined relative function call. At runtime, when X-Ray is enabled, the sled is replaced by compiler-rt with a trampoline to the logic for creating the custom log entries. Future patches will implement the compiler-rt parts and clang-side support for emitting the IR corresponding to this intrinsic. Reviewers: timshen, dberris Subscribers: igorb, pelikan, rSerge, timshen, echristo, dberris, llvm-commits Differential Revision: https://reviews.llvm.org/D27503 llvm-svn: 302405
* [DAGCombiner] If ISD::ABS is legal/custom, use it directly instead of ↵Simon Pilgrim2017-05-061-0/+3
| | | | | | | | | | canonicalizing first. Remove an extra canonicalization step if ISD::ABS is going to be used anyway. Updated x86 abs combine to check that we are lowering from both canonicalizations. llvm-svn: 302337
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-052-28/+68
| | | | | | | | | | This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-055-8/+39
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* [CodeView] Reserve TypeDatabase records up front.Zachary Turner2017-05-051-1/+1
| | | | | | | | | | | | | Most of the time we know exactly how many type records we have in a list, and we want to use the visitor to deserialize them into actual records in a database. Previously we were just using push_back() every time without reserving the space up front in the vector. This is obviously terrible from a performance standpoint, and it's not uncommon to have PDB files with half a million type records, where the performance degredation was quite noticeable. llvm-svn: 302302
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-054-44/+107
| | | | | | | | | | | | | | | | | - MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 llvm-svn: 302289
* Simplify dbg.value handling in SDISel with early returnsReid Kleckner2017-05-051-35/+23
| | | | | | | | | | | | | | No functional change other than improving dbgs logging accuracy on constant dbg values. Previously we would add things like "i32 42" as debug values, and then log that we were dropping the debug info, which is silly. Delete some dead code that was checking for static allocas. This remained after r207165, but served no purpose. Currently, static alloca dbg.values are always sent through the DanglingDebugInfoMap, and are usually made valid the first time the alloca is used. llvm-svn: 302267
* [KnownBits] Add wrapper methods for setting and clear all bits in the ↵Craig Topper2017-05-052-7/+4
| | | | | | | | | | underlying APInts in KnownBits. This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown. Differential Revision: https://reviews.llvm.org/D32637 llvm-svn: 302262
* Remove stale live-ins in the branch folderKrzysztof Parzyszek2017-05-051-12/+22
| | | | | | | | | | | Hoisting common code can cause registers that live-in in the successor blocks to no longer be live-in. The live-in information needs to be updated to reflect this, or otherwise incorrect code can be generated later on. Differential Revision: https://reviews.llvm.org/D32661 llvm-svn: 302228
* [GISel]:Skip legalizing Intermediate inst(with generic types)Aditya Nandakumar2017-05-041-2/+7
| | | | | | | | | | During legalization, targets can create Pseudo Instructions with generic types. We shouldn't try to legalize them. Reviewed by Quentin, dsanders https://reviews.llvm.org/D32575 llvm-svn: 302199
* [GISel]: Add support to translate ConstantVectorsAditya Nandakumar2017-05-041-0/+8
| | | | | | | Reviewed by Quentin https://reviews.llvm.org/D32814 llvm-svn: 302196
* [DAGCombine] Transform (fadd A, (fmul B, -2.0)) -> (fsub A, (fadd B, B)).Chad Rosier2017-05-041-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D32596 llvm-svn: 302153
* Refactoring with range-based for, NFCKrzysztof Parzyszek2017-05-043-119/+94
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D32682 llvm-svn: 302148
* [XRay] Use wordsize-dependent alignment for indexDean Michael Berris2017-05-041-3/+3
| | | | | | | | | | This makes it simpler for the runtime to consistently handle the entries in the function sled index in both 32 and 64 bit platforms where the XRay runtime works. Follow-up on D32693. llvm-svn: 302111
* [SelectionDAG] Improve known bits support for CTPOP.Craig Topper2017-05-041-1/+4
| | | | | | This is based on the same concept from ValueTracking's version of computeKnownBits. llvm-svn: 302110
* [XRay] Create an Index of sleds per functionDean Michael Berris2017-05-041-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change adds a new section to the xray-instrumented binary that stores an index into ranges of the instrumentation map, where sleds associated with the same function can be accessed as an array. At runtime, we can get access to this index by function ID offset allowing for selective patching and unpatching by function ID. Each entry in this new section (xray_fn_idx) will include two pointers indicating the start and one past the end of the sleds associated with the same function. These entries will be 16 bytes long on x86 and aarch64. On arm, we align to 16 bytes anyway so the runtime has to take that into consideration. __{start,stop}_xray_fn_idx will be the symbols that the runtime will look for when we implement the selective patching/unpatching by function id APIs. Because XRay synthesizes the function id's in a monotonically increasing manner at runtime now, implementations (and users) can use this table to look up the sleds associated with a specific function. This is useful in implementations that want to do things like: - Implement coverage mode for functions by patching everything pre-main, then as functions are encountered, the installed handler can unpatch the function that's been encountered after recording that it's been called. - Do "learning mode", so that the implementation can figure out some statistical information about function calls by function id for a time being, and then determine which functions are worth uninstrumenting at runtime. - Do "selective instrumentation" where an implementation can specifically instrument only certain function id's at runtime (either based on some external data, or through some other heuristics) instead of patching all the instrumented functions at runtime. Reviewers: dblaikie, echristo, chandlerc, javed.absar Subscribers: pelikan, aemerson, kpw, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D32693 llvm-svn: 302109
* [XRay] Detect loops in functions being loweredDean Michael Berris2017-05-041-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is an implementation of the loop detection logic that XRay needs to determine whether a function might take time at runtime. Without this heuristic, XRay will tend to not instrument short functions that have loops that might have runtime dependent on inputs or external values. While this implementation doesn't do any further analysis than just figuring out whether there is a loop in the MachineFunction being code-gen'ed, we're paving the way for being able to perform more sophisticated analysis of the function in the future (for example to determine whether the trip count for the loop might be constant, and make a decision on that instead). This enables us to cover more functions with the default heuristics, and potentially identify ones that have variable runtime latency just by looking for the presence of loops. Reviewers: chandlerc, rnk, pelikan Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32274 llvm-svn: 302103
* [KnownBits] Add zext, sext, and trunc methods to KnownBitsCraig Topper2017-05-033-44/+22
| | | | | | | | This patch adds zext, sext, and trunc methods to KnownBits and uses them where possible. Differential Revision: https://reviews.llvm.org/D32784 llvm-svn: 302088
* [TargetLowering] use isSubsetOf in SimplifyDemandedBits; NFCISanjay Patel2017-05-031-18/+14
| | | | | | | | | This is the DAG equivalent of https://reviews.llvm.org/D32255 , which will hopefully be committed again. The functionality (preferring a 'not' op) is already here in the DAG, so this is just intended to be a clean-up and performance improvement. llvm-svn: 302087
* DebugInfo: elide type index entries for synthetic typesSaleem Abdulrasool2017-05-031-4/+6
| | | | | | | | | | | | | | Compiler emitted synthetic types may not have an associated DIFile (translation unit). In such a case, when generating CodeView debug type information, we would attempt to compute an absolute filepath which would result in a segfault due to a NULL DIFile*. If there is no source file associated with the type, elide the type index entry for the type and record the type information. This actually results in higher fidelity debug information than clang/C2 as of this writing. Resolves PR32668! llvm-svn: 302085
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