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* Reapply r276973 "Adjust Registry interface to not require plugins to export ↵John Brawn2016-08-052-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a registry" This differs from the previous version by being more careful about template instantiation/specialization in order to prevent errors when building with clang -Werror. Specifically: * begin is not defined in the template and is instead instantiated when Head is. I think the warning when we don't do that is wrong (PR28815) but for now at least do it this way to avoid the warning. * Instead of performing template specializations in LLVM_INSTANTIATE_REGISTRY instead provide a template definition then do explicit instantiation. No compiler I've tried has problems with doing it the other way, but strictly speaking it's not permitted by the C++ standard so better safe than sorry. Original commit message: Currently the Registry class contains the vestiges of a previous attempt to allow plugins to be used on Windows without using BUILD_SHARED_LIBS, where a plugin would have its own copy of a registry and export it to be imported by the tool that's loading the plugin. This only works if the plugin is entirely self-contained with the only interface between the plugin and tool being the registry, and in particular this conflicts with how IR pass plugins work. This patch changes things so that instead the add_node function of the registry is exported by the tool and then imported by the plugin, which solves this problem and also means that instead of every plugin having to export every registry they use instead LLVM only has to export the add_node functions. This allows plugins that use a registry to work on Windows if LLVM_EXPORT_SYMBOLS_FOR_PLUGINS is used. llvm-svn: 277806
* GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.Tim Northover2016-08-041-2/+8
| | | | | | | These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
* GlobalISel: add support for G_MULTim Northover2016-08-041-0/+2
| | | | llvm-svn: 277774
* GlobalISel: implement narrowing for G_ADD.Tim Northover2016-08-042-1/+49
| | | | llvm-svn: 277769
* GlobalISel: also add G_TRUNC to IRTranslator.Tim Northover2016-08-041-1/+3
| | | | llvm-svn: 277749
* GlobalISel: add code to widen scalar G_ADDTim Northover2016-08-043-1/+39
| | | | llvm-svn: 277747
* [X86] Heuristic to selectively build Newton-Raphson SQRT estimationNikolai Bozhenov2016-08-042-3/+6
| | | | | | | | | | | | | | | | | | | | | On modern Intel processors hardware SQRT in many cases is faster than RSQRT followed by Newton-Raphson refinement. The patch introduces a simple heuristic to choose between hardware SQRT instruction and Newton-Raphson software estimation. The patch treats scalars and vectors differently. The heuristic is that for scalars the compiler should optimize for latency while for vectors it should optimize for throughput. It is based on the assumption that throughput bound code is likely to be vectorized. Basically, the patch disables scalar NR for big cores and disables NR completely for Skylake. Firstly, scalar SQRT has shorter latency than NR code in big cores. Secondly, vector SQRT has been greatly improved in Skylake and has better throughput compared to NR. Differential Revision: https://reviews.llvm.org/D21379 llvm-svn: 277725
* Typo fix in comment. NFCDiana Picus2016-08-041-1/+1
| | | | llvm-svn: 277704
* RenameIndependentSubregs: Fix liveness query in rewriteOperands()Matthias Braun2016-08-031-7/+6
| | | | | | | | rewriteOperands() always performed liveness queries at the base index rather than the RegSlot/Base as apropriate for the machine operand. This could lead to illegal rewriting in some cases. llvm-svn: 277661
* Disable shrinking of SNaN constantsElliot Colp2016-08-031-11/+17
| | | | | | | | | When expanding FP constants, we attempt to shrink doubles to floats and perform an extending load. However, on SystemZ, and possibly on other targets (I've only confirmed the problem on SystemZ), the FP extending load instruction may convert SNaN into QNaN, or may cause an exception. So in the general case, we would still like to shrink FP constants, but SNaNs should be left as doubles. Differential Revision: https://reviews.llvm.org/D22685 llvm-svn: 277602
* [IfConversion] Bugfix: Don't use undef flag while adding use operands.Jonas Paulsson2016-08-031-3/+16
| | | | | | | | | | | | | | | | | IfConversion used to always add the undef flag when adding a use operand on a newly predicated instruction. This would be an operand for the register being conditionally redefined. Due to the undef flag, the liveness of this register prior to the predicated instruction would get lost. This patch changes this so that such use operands are added only when the register is live, without the undef flag. This was reverted but pushed again now, for details follow link below. Reviewed by Quentin Colombet. http://reviews.llvm.org/D209077 llvm-svn: 277571
* [safestack] Layout large allocas first to reduce fragmentation.Evgeniy Stepanov2016-08-021-0/+8
| | | | llvm-svn: 277544
* [GlobalISel] Set the Selected MF property.Ahmed Bougacha2016-08-021-14/+0
| | | | | | | None of GlobalISel requires the property, but this lets us use the verifier instead of rolling our own "all instructions selected" check. llvm-svn: 277484
* [GlobalISel] Verify Selected MF property.Ahmed Bougacha2016-08-021-1/+15
| | | | | | | | After instruction selection, there should be no pre-isel generic instructions remaining, nor should generic virtual registers be used. Verify that. llvm-svn: 277483
* [GlobalISel] Add Selected MachineFunction property.Ahmed Bougacha2016-08-023-0/+7
| | | | | | | | | | | | | | | | Selected: the InstructionSelect pass ran and all pre-isel generic instructions have been eliminated; i.e., all instructions are now target-specific or non-pre-isel generic instructions (e.g., COPY). Since only pre-isel generic instructions can have generic virtual register operands, this also means that all generic virtual registers have been constrained to virtual registers (assigned to register classes) and that all sizes attached to them have been eliminated. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277482
* [GlobalISel] Verify RegBankSelected MF property.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
* [GlobalISel] Add RegBankSelected MachineFunction property.Ahmed Bougacha2016-08-023-0/+8
| | | | | | | | | | RegBankSelected: the RegBankSelect pass ran and all generic virtual registers have been assigned to a register bank. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277475
* [GlobalISel] Set, require, and verify Legalized MF property.Ahmed Bougacha2016-08-022-0/+35
| | | | | | | | | | | | | RegBankSelect and InstructionSelect run after the legalizer and require a Legalized function: check that all instructions are legal. Note that this should be in the MachineVerifier, but it can't use the MachineLegalizer as it's currently in the separate GlobalISel library. Note that the RegBankSelect verifier checks have the same layering problem, but we only use inline methods so end up not needing to link against the GlobalISel library. llvm-svn: 277472
* [GlobalISel] Add Legalized MachineFunction property.Ahmed Bougacha2016-08-023-0/+10
| | | | | | | | | | | | | Legalized: The MachineLegalizer ran; all pre-isel generic instructions have been legalized, i.e., all instructions are now one of: - generic and always legal (e.g., COPY) - target-specific - legal pre-isel generic instructions. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277470
* [CodeGen] Generalize MachineFunctionProperties::print comma handling.Ahmed Bougacha2016-08-021-2/+7
| | | | | | | | This is only used for debug prints, but the previous hardcoded ", " caused it to be printed unnecessarily when OnlySet, and is annoying when adding new properties. llvm-svn: 277465
* [GlobalISel] Don't RegBankSelect target-specific instructions.Ahmed Bougacha2016-08-021-1/+7
| | | | | | They don't have types and should be using register classes. llvm-svn: 277447
* [GlobalISel] Don't legalize non-generic instructions.Ahmed Bougacha2016-08-021-0/+6
| | | | | | They don't have types and should be legal. llvm-svn: 277446
* [GlobalISel] Const-ify MachineInstrs passed to MachineLegalizer.Ahmed Bougacha2016-08-021-2/+2
| | | | llvm-svn: 277445
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-021-0/+6
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277411
* [DAGCombine] Make sext(setcc) combine respect getBooleanContentsMichael Kuperstein2016-08-012-9/+33
| | | | | | | | | | | We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)" Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value of T is 1 or -1, depending on the type of the setcc, and getBooleanContents() for the type if it is not i1. This fixes PR28504. llvm-svn: 277371
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-011-9/+9
| | | | | | There were a few cases introduced with the modulo scheduler. llvm-svn: 277358
* Revert r277313 and r277314.Sean Silva2016-08-011-6/+0
| | | | | | | | | | | | | | | They seem to trigger an LSan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio Revert "Add the tests for r277313" This reverts commit r277314. Revert "CodeExtractor : Add ability to preserve profile data." This reverts commit r277313. llvm-svn: 277317
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-011-0/+6
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277313
* DAG: avoid duplicated truncating for sign extended operandWeiming Zhao2016-07-291-8/+10
| | | | | | | | | | | | | | | Summary: When performing cmp for EQ/NE and the operand is sign extended, we can avoid the truncaton if the bits to be tested are no less than origianl bits. Reviewers: eli.friedman Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D22933 llvm-svn: 277252
* GlobalISel: translate "unreachable" (into nothing)Tim Northover2016-07-291-0/+3
| | | | | | Easiest instruction ever! llvm-svn: 277225
* GlobalISel: support translation of intrinsic calls.Tim Northover2016-07-292-0/+48
| | | | | | | | These come in two variants for now: G_INTRINSIC and G_INTRINSIC_W_SIDE_EFFECTS. We may decide to split the latter up with finer-grained restrictions later, if necessary. llvm-svn: 277224
* [msf] Resubmit "Rename Msf -> MSF".Zachary Turner2016-07-292-3/+3
| | | | | | | | | | | | | Previously this change was submitted from a Windows machine, so changes made to the case of filenames and directory names did not survive the commit, and as a result the CMake source file names and the on-disk file names did not match on case-sensitive file systems. I'm resubmitting this patch from a Linux system, which hopefully allows the case changes to make it through unfettered. llvm-svn: 277213
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-295-5/+74
| | | | | | | This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209
* Fixed (incorrectly firing) MSVC unused variable warningSimon Pilgrim2016-07-291-2/+1
| | | | llvm-svn: 277198
* Revert "[msf] Rename Msf to MSF."Zachary Turner2016-07-292-3/+3
| | | | | | This reverts commit 4d1557ffac41e079bcb1abbcf04f512474dcd6fe. llvm-svn: 277194
* [msf] Rename Msf to MSF.Zachary Turner2016-07-292-3/+3
| | | | | | | | In a previous patch, it was suggested to use all caps instead of rolling caps for initialisms, so this patch changes everything to do this. llvm-svn: 277190
* Recommitting r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-292-0/+48
| | | | | | | | Patch by Sunita Marathe Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan buildbots. (Thanks, Evegenii!) llvm-svn: 277189
* GlobalISel: make translate* functions take the most specialized class possible.Tim Northover2016-07-291-15/+14
| | | | | | NFC. llvm-svn: 277188
* Codegen: MachineBlockPlacement Improve probability layout.Kyle Butt2016-07-291-15/+45
| | | | | | | | | | | | | | | | | | | | | | | | | The following pattern was being layed out poorly: A / \ B C / \ / \ D E ? (Doesn't matter) Where A->B is far more likely than A->C, and prob(B->D) = prob(B->E) The current algorithm gives: A,B,C,E (D goes on worklist) It does this even if C has a frequency count of 0. This patch adjusts the layout calculation so that if freq(B->E) >> freq(C->E) then we go ahead and layout E rather than C. Fallthrough half the time is better than fallthrough never, or fallthrough very rarely. The resulting layout is: A,B,E, (C and D are in a worklist) llvm-svn: 277187
* GlobalISel: add generic conditional branch.Tim Northover2016-07-292-7/+20
| | | | | | | Just the basic equivalent to DAG's condbr for now, we'll get to things like br_cc when we start doing more legalization. llvm-svn: 277184
* CodeGen: improve MachineInstrBuilder & MachineIRBuilder interfaceTim Northover2016-07-292-50/+54
| | | | | | | | | | | | | | For MachineInstrBuilder, having to manually use RegState::Define is ugly and makes register definitions clunkier than they need to be, so this adds two convenience functions: addDef and addUse. For MachineIRBuilder, we want to avoid BuildMI's first-reg-is-def rule because it's hidden away and causes bugs. So this patch switches buildInstr to returning a MachineInstrBuilder and adding *all* operands via addDef/addUse. NFC. llvm-svn: 277176
* [GlobalISel] Add G_XOR.Ahmed Bougacha2016-07-291-0/+2
| | | | llvm-svn: 277172
* [AArch64][GlobalISel] Select G_LOAD/G_STORE.Ahmed Bougacha2016-07-291-2/+6
| | | | | | | | | | Mostly straightforward as we ignore addressing modes and just use the base + unsigned immediate offset (always 0) variants. This currently fails to select extloads because we have yet to agree on a representation. llvm-svn: 277171
* MachinePipeliner pass that implements Swing Modulo SchedulingBrendon Cahoon2016-07-293-0/+3945
| | | | | | | | | | | | | | | | | | | | | | | | Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
* Cleanup TransferDbgValuesNirav Dave2016-07-291-2/+9
| | | | | | | | | | | | | | | [DAG] Check debug values for invalidation before transferring and mark old debug values invalid when transferring to another SDValue. This fixes PR28613. Reviewers: jyknight, hans, dblaikie, echristo Subscribers: yaron.keren, ismail, llvm-commits Differential Revision: https://reviews.llvm.org/D22858 llvm-svn: 277135
* [ConstnatFolding] Teach the folder how to fold ConstantVectorDavid Majnemer2016-07-291-2/+2
| | | | | | | | | | | A ConstantVector can have ConstantExpr operands and vice versa. However, the folder had no ability to fold ConstantVectors which, in some cases, was an optimization barrier. Instead, rephrase the folder in terms of Constants instead of ConstantExprs and teach callers how to deal with failure. llvm-svn: 277099
* Revert "Don't invoke getName() from Function::isIntrinsic().", rL276942.Justin Lebar2016-07-281-6/+2
| | | | | | | | | This broke some out-of-tree AMDGPU tests that relied on the old behavior wherein isIntrinsic() would return true for any function that starts with "llvm.". And in general that change will not play nicely with out-of-tree backends. llvm-svn: 277087
* Missed updating a GlobalISel bit in my last commitMatthias Braun2016-07-281-1/+1
| | | | | | GlobalISel isn't built by default so I missed it. llvm-svn: 277030
* Fix DbgValue handling in SelectionDAG.Nirav Dave2016-07-281-2/+3
| | | | | | | [DAG] Relocate TransferDbgValues in ReplaceAllUsesWith(SDValue, SDValue) to before we modify the CSE maps. llvm-svn: 277027
* [pdb] Refactor library to more clearly separate reading/writingZachary Turner2016-07-281-1/+1
| | | | | | | Reviewed By: amccarth, ruiu Differential Revision: https://reviews.llvm.org/D22693 llvm-svn: 277019
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