| Commit message (Collapse) | Author | Age | Files | Lines |
| ... | |
| |
|
|
| |
llvm-svn: 78601
|
| |
|
|
|
|
| |
SimpleValueType, which will simplify the privatization of IntegerType in the future.
llvm-svn: 78584
|
| |
|
|
| |
llvm-svn: 78569
|
| |
|
|
|
|
|
|
|
|
| |
This definitely slows down asm output so put it under an -asm-exuberant
flag.
This information is useful when doing static analysis of performance
issues.
llvm-svn: 78567
|
| |
|
|
|
|
| |
target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
llvm-svn: 78563
|
| |
|
|
|
|
| |
add support for PtrToInt, Add, Mul.
llvm-svn: 78552
|
| |
|
|
|
|
|
|
| |
classes.
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
llvm-svn: 78517
|
| |
|
|
|
|
|
|
|
| |
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
|
| |
|
|
|
|
|
|
| |
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
llvm-svn: 78498
|
| |
|
|
|
|
|
|
| |
Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.
llvm-svn: 78497
|
| |
|
|
|
|
|
|
|
|
|
| |
Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations
llvm-svn: 78476
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Also don't dereference old pointers after they have been deleted causing
random crashes when enabling the machine code verifier.
Ahem...
I have not included a test case for the crash. It hapened when enabling the
verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll.
The crash depends on an MBB being allocated at the same address as a
previously deleted MBB. I don't think that can be reproduced reliably.
llvm-svn: 78472
|
| |
|
|
|
|
|
|
|
| |
* Cleaner handling of <undef>.
* <def> takes precedence over <def,dead>.
* Implement the OK-to-redefine-a-register-that-was-
live-in-but-has-not-been-used-before rule.
llvm-svn: 78467
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
mistaken commit r77904.
Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>
llvm-svn: 78466
|
| |
|
|
|
|
|
|
|
|
|
| |
Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
|
| |
|
|
| |
llvm-svn: 78447
|
| |
|
|
| |
llvm-svn: 78432
|
| |
|
|
| |
llvm-svn: 78428
|
| |
|
|
|
|
| |
number of ARM tests.
llvm-svn: 78421
|
| |
|
|
| |
llvm-svn: 78416
|
| |
|
|
|
|
| |
preference; no functional change.
llvm-svn: 78391
|
| |
|
|
|
|
| |
a def of the exact register rather than a super-register.
llvm-svn: 78376
|
| |
|
|
| |
llvm-svn: 78367
|
| |
|
|
| |
llvm-svn: 78363
|
| |
|
|
| |
llvm-svn: 78362
|
| |
|
|
| |
llvm-svn: 78360
|
| |
|
|
|
|
| |
stuff as it was only meant for debugging the solver.
llvm-svn: 78359
|
| |
|
|
|
|
| |
based solver, but I'll be working to improve that. The PBQP allocator has been updated to use the new solver.
llvm-svn: 78354
|
| |
|
|
|
|
| |
produced a CFG it wasn't prepared for.
llvm-svn: 78351
|
| |
|
|
| |
llvm-svn: 78350
|
| |
|
|
|
|
| |
If we need it one day, there is nothing wrong with putting it back in.
llvm-svn: 78337
|
| |
|
|
|
|
|
| |
- start support for new PEI w/reg alloc, allow running RS from emit{Pro,Epi}logue() target hooks.
- fix minor issue with recursion detection.
llvm-svn: 78318
|
| |
|
|
|
|
|
| |
and LowerReturn, to verify that the targets' hooks have respected some
of their postconditions.
llvm-svn: 78312
|
| |
|
|
|
|
|
| |
types don't have any return values, from CodeGen's perspective.
This fixes PR4688.
llvm-svn: 78311
|
| |
|
|
|
|
|
|
| |
and high-bits values in ways that weren't correct for integer
types wider than 64 bits. This fixes a miscompile in
PPMacroExpansion.cpp in clang on x86-64.
llvm-svn: 78295
|
| |
|
|
|
|
| |
contexts through a number of APIs.
llvm-svn: 78258
|
| |
|
|
|
|
| |
and eliminate complexity. Yay!
llvm-svn: 78243
|
| |
|
|
| |
llvm-svn: 78242
|
| |
|
|
| |
llvm-svn: 78202
|
| |
|
|
| |
llvm-svn: 78179
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
After coalescing reg1027's def and kill are both at the same point:
%reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
bb5:
60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
Do not remove the kill marker on t2LDRi12.
llvm-svn: 78178
|
| |
|
|
| |
llvm-svn: 78177
|
| |
|
|
|
|
|
|
|
|
|
|
| |
a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
llvm-svn: 78176
|
| |
|
|
| |
llvm-svn: 78154
|
| |
|
|
| |
llvm-svn: 78151
|
| |
|
|
| |
llvm-svn: 78145
|
| |
|
|
| |
llvm-svn: 78144
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
|
| |
|
|
|
|
| |
copy.
llvm-svn: 78141
|
| |
|
|
| |
llvm-svn: 78139
|