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* [MC] Move .cv_loc management logic out of MCContextReid Kleckner2016-08-263-2/+5
| | | | | | | | | | | MCContext already has many tasks, and separating CodeView out from it is probably a good idea. The .cv_loc tracking was modelled on the DWARF tracking which lived directly in MCContext. Removes the inclusion of MCCodeView.h from MCContext.h, so now there are only 10 build actions while I hack on CodeView support instead of 265. llvm-svn: 279847
* GlobalISel: simplify G_ICMP legalization regime.Tim Northover2016-08-261-30/+20
| | | | | | | | | | | | | | It's unclear how the old %res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1 is actually different from an s1 verison %res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1 so we'll remove it for now. llvm-svn: 279843
* GlobalISel: legalize sdiv and srem operations.Tim Northover2016-08-263-0/+46
| | | | llvm-svn: 279842
* GlobalISel: legalize under-width divisions.Tim Northover2016-08-261-0/+27
| | | | llvm-svn: 279841
* Missed a semicolon in r279835Krzysztof Parzyszek2016-08-261-1/+1
| | | | llvm-svn: 279836
* Add some more detailed debugging information in RegisterCoalescerKrzysztof Parzyszek2016-08-261-5/+19
| | | | llvm-svn: 279835
* Replace subregister uses when processing tied operandsMatt Arsenault2016-08-261-2/+2
| | | | | | | | | | | | | | | | | | | | | This was for some reason skipping operands that are subregisters instead of keeping the same subregister index. v_movreld_b32 expects src0 to be the subregister of the tied super register use/def. e.g. v_movreld_b32 v0, v9, <imp-def, tied3> v[0:3], <imp-use, tied2> v[0:3] was being replaced with v[4:7] = copy v[0:3] v_movreld_b32 v0, v9, <imp-def, tied3> v[4:7], <imp-use, tied2> v[4:7], which really writes to v[0:3] llvm-svn: 279804
* Reuse an SDLoc throughout a function. NFC.Michael Kuperstein2016-08-251-18/+12
| | | | llvm-svn: 279767
* GlobalISel: add missing type to G_UADDE instructionsTim Northover2016-08-251-5/+4
| | | | llvm-svn: 279762
* GlobalISel: perform multi-step legalizationTim Northover2016-08-252-2/+41
| | | | llvm-svn: 279758
* Make buildbots happy.George Burgess IV2016-08-251-1/+1
| | | | | | "warning: extra ‘;’ [-Wpedantic]" llvm-svn: 279703
* TailDuplication: Don't pass MMI separately from MF. NFCKyle Butt2016-08-252-3/+2
| | | | | | | MMI must match the function passed, and MF has a handle on MMI. Use that instead of accepting it as separate argument. No Functional Change. llvm-svn: 279701
* TailDuplication: Save MF and reduce number of parameters. NFCKyle Butt2016-08-252-24/+22
| | | | | | | | Save the function in the class, and then don't pass it around. This reduces the number of parameters and makes calls to member functions simpler. No Functional Change. llvm-svn: 279700
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-2516-24/+21
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* Make some LLVM_CONSTEXPR variables const. NFC.George Burgess IV2016-08-251-1/+1
| | | | | | | | | | This patch changes LLVM_CONSTEXPR variable declarations to const variable declarations, since LLVM_CONSTEXPR expands to nothing if the current compiler doesn't support constexpr. In all of the changed cases, it looks like the code intended the variable to be const instead of sometimes-constexpr sometimes-not. llvm-svn: 279696
* Fix some Clang-tidy modernize-use-using and Include What You Use warnings; ↵Eugene Zelenko2016-08-254-21/+63
| | | | | | | | other minor fixes. Differential revision: https://reviews.llvm.org/D23861 llvm-svn: 279695
* MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing itMatthias Braun2016-08-242-11/+13
| | | | llvm-svn: 279680
* MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not ↵Matthias Braun2016-08-246-14/+10
| | | | | | | | | | | | | print/parser it tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there is not need to change it or save/parse it in a .mir file. Make the field const and move the initialization LiveIntervalAnalysis to the MachineRegisterInfo constructor. Also cleanup some code and fix some instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead of TargetSubtargetInfo::enableSubRegLiveness(). llvm-svn: 279676
* CodeGen: If Convert blocks that would form a diamond when tail-merged.Kyle Butt2016-08-241-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following function currently relies on tail-merging for if conversion to succeed. The common tail of cond_true and cond_false is extracted, and this then forms a diamond pattern that can be successfully if converted. If this block does not get extracted, either because tail-merging is disabled or the threshold is higher, we should still recognize this pattern and if-convert it. Fixed a regression in the original commit. Need to un-reverse branches after reversing them, or other conversions go awry. define i32 @t2(i32 %a, i32 %b) nounwind { entry: %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] br i1 %tmp1434, label %bb17, label %bb.outer bb.outer: ; preds = %cond_false, %entry %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] br label %bb bb: ; preds = %cond_true, %bb.outer %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] %tmp. = sub i32 0, %b_addr.021.0.ph %tmp.40 = mul i32 %indvar, %tmp. %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph br i1 %tmp3, label %cond_true, label %cond_false cond_true: ; preds = %bb %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph %indvar.next = add i32 %indvar, 1 br i1 %tmp1437, label %bb17, label %bb cond_false: ; preds = %bb %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 br i1 %tmp14, label %bb17, label %bb.outer bb17: ; preds = %cond_false, %cond_true, %entry %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ret i32 %a_addr.026.1 } Without tail-merging or diamond-tail if conversion: LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ble LBB1_3 @ BB#2: @ %cond_true @ in Loop: Header=BB1_1 Depth=1 subs r0, r0, r1 cmp r1, r0 it ne cmpne r0, r1 bgt LBB1_4 LBB1_3: @ %cond_false @ in Loop: Header=BB1_1 Depth=1 subs r1, r1, r0 cmp r1, r0 bne LBB1_1 LBB1_4: @ %bb17 bx lr With diamond-tail if conversion, but without tail-merging: @ BB#0: @ %entry cmp r0, r1 it eq bxeq lr LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ite le suble r1, r1, r0 subgt r0, r0, r1 cmp r1, r0 bne LBB1_1 @ BB#2: @ %bb17 bx lr llvm-svn: 279671
* IfConversion: Rescan diamonds.Kyle Butt2016-08-241-52/+162
| | | | | | | | | | | | | | | | The cost of predicating a diamond is only the instructions that are not shared between the two branches. Additionally If a predicate clobbering instruction occurs in the shared portion of the branches (e.g. a cond move), it may still be possible to if convert the sub-cfg. This change handles these two facts by rescanning the non-shared portion of a diamond sub-cfg to recalculate both the predication cost and whether both blocks are pred-clobbering. Fixed 2 bugs before recommitting. Branch instructions must be compared and found identical before diamond conversion. Also, predicate-clobbering instructions in the shared prefix disqualifies a potential diamond conversion. Includes tests for both. llvm-svn: 279670
* DebugInfo: Add flag to CU to disable emission of inline debug info into the ↵David Blaikie2016-08-241-2/+4
| | | | | | | | | | skeleton CU In cases where .dwo/.dwp files are guaranteed to be available, skipping the extra online (in the .o file) inline info can save a substantial amount of space - see the original r221306 for more details there. llvm-svn: 279650
* Create subranges for new intervals resulting from live interval splittingKrzysztof Parzyszek2016-08-2412-156/+652
| | | | | | | | | | | | | | | | | | | The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
* TargetSchedule: Do not consider subregister definitions as reads.Matthias Braun2016-08-241-1/+1
| | | | | | | | | | | | | | We should not consider subregister definitions as reads for schedule model purposes (they are just modeled as reads of the overal vreg for liveness calculation purposes, the CPU instructions are not actually reading). Unfortunately I cannot submit a test for this as it requires a target which uses ReadAdvance annotation in the scheduling model and has subregister liveness enabled at the same time, which is only the case on an out of tree target. llvm-svn: 279604
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-246-78/+74
| | | | | | | | | | | | | | | | | | | | | | Re-apply this patch, hopefully I will get away without any warnings in the constructor now. This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279602
* MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.Matthias Braun2016-08-243-6/+19
| | | | | | | | | Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 llvm-svn: 279600
* MachineModuleInfo: Avoid dummy constructor, use INITIALIZE_TM_PASSMatthias Braun2016-08-242-24/+10
| | | | | | | | | | | Change this pass constructor to just accept a const TargetMachine * and use INITIALIZE_TM_PASS, that way we can get rid of the dummy constructor. The pass will still fail when calling the default constructor leading to TM == nullptr, this is no different than before but is more in line what other codegen passes are doing and avoids the dummy constructor. llvm-svn: 279598
* [stackmaps] Remove an unneeded member variable [NFC]Philip Reames2016-08-231-2/+1
| | | | llvm-svn: 279590
* [stackmaps] More extraction of common code [NFCI]Philip Reames2016-08-231-6/+5
| | | | | | General cleanup before starting to work on the part I want to actually change. llvm-svn: 279586
* Don't use "return {...}" to initialize a std::tuple. This has only been validRichard Smith2016-08-231-2/+2
| | | | | | | | | since 2015 (n4387), though it's allowed by a library DR so new implementations accept it in their C++11 modes... This should unbreak the build with libstdc++ 4.9. llvm-svn: 279583
* #ifdef out validation code when asserts are disabled to remove unused variableRichard Smith2016-08-231-0/+2
| | | | | | warnings. llvm-svn: 279582
* Remove unused data member to unbreak -Werror builds.Richard Smith2016-08-231-2/+1
| | | | llvm-svn: 279581
* Revert r279564. It introduces undefined behavior (binding a reference to aRichard Smith2016-08-237-83/+86
| | | | | | | dereferenced null pointer) in MachineModuleInfo::MachineModuleInfo that causes -Werror builds (including several buildbots) to fail. llvm-svn: 279580
* [stackmaps] Extract out magic constants [NFCI]Philip Reames2016-08-232-6/+17
| | | | | | This is a first step towards clarifying the exact MI semantics of stackmap's "live values". llvm-svn: 279574
* MachineFunction: Introduce NoPHIs propertyMatthias Braun2016-08-238-2/+45
| | | | | | | | | | | | | I want to compute the SSA property of .mir files automatically in upcoming patches. The problem with this is that some inputs will be reported as static single assignment with some passes claiming not to support SSA form. In reality though those passes do not support PHI instructions => Track the presence of PHI instructions separate from the SSA property. Differential Revision: https://reviews.llvm.org/D22719 llvm-svn: 279573
* GlobalISel: make truncate/extend casts uniformTim Northover2016-08-233-21/+46
| | | | | | | They really should have both types represented, but early variants were created before MachineInstrs could have multiple types so they're rather ambiguous. llvm-svn: 279567
* GlobalISel: legalize integer comparisons on AArch64.Tim Northover2016-08-233-3/+45
| | | | | | | Next step is doing both legalizations at the same time! Marvel at GlobalISel's cunning. llvm-svn: 279566
* GlobalISel: legalize conditional branches on AArch64.Tim Northover2016-08-232-0/+12
| | | | llvm-svn: 279565
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-237-86/+83
| | | | | | | | | | | | | | | | | | | | | | | Re-apply this commit with the deletion of a MachineFunction delegated to a separate pass to avoid use after free when doing this directly in AsmPrinter. This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279564
* GlobalISel: extend legalizer interface to handle multiple types.Tim Northover2016-08-232-30/+45
| | | | | | | | Instructions like G_ICMP have multiple types that may need to be legalized (the boolean output and nearly arbitrary inputs in this case). So the legalizer must be capable of deciding what to do for each of them separately. llvm-svn: 279554
* GlobalISel: legalize 1-bit load/store and mark 8/16 bit variants legal on ↵Tim Northover2016-08-231-5/+24
| | | | | | AArch64. llvm-svn: 279548
* [SelectionDAG] Use a union of bitfield structs for SDNode::SubclassData.Justin Lebar2016-08-231-43/+18
| | | | | | | | | | | | | | | | | | Summary: This greatly simplifies our handling of SDNode::SubclassData. NFC, hopefully. :) See discussion in D23035 for discussion about the design API of these bitfields. Reviewers: chandlerc Subscribers: llvm-commits, rnk Differential Revision: https://reviews.llvm.org/D23036 llvm-svn: 279537
* [CodeGen] Convert a loop to a for-each loop. NFCJustin Lebar2016-08-231-7/+5
| | | | llvm-svn: 279536
* Fix some more asserts after r279466.Pete Cooper2016-08-233-3/+3
| | | | | | | | | | | | | | | | That commit added a new version of Intrinsic::getName which should only be called when the intrinsic has no overloaded types. There are several debugging paths, such as SDNode::dump which are printing the name of the intrinsic but don't have the overloaded types. These paths should be ok to just print the name instead of crashing. The fix here is ultimately to just add a 'None' second argument as that calls the overload capable getName, which is less efficient, but this is a debugging path anyway, and not perf critical. Thanks to Björn Pettersson for pointing out that there were more crashes. llvm-svn: 279528
* Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: Remove ↵Matthias Braun2016-08-237-67/+84
| | | | | | | | | | MachineFunctionAnalysis => Enable (Machine)ModulePasses" Reverting while tracking down a use after free. This reverts commit r279502. llvm-svn: 279503
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-237-84/+67
| | | | | | | | | | | | | | | | | | | This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279502
* Fix crash from assert in r279466.Pete Cooper2016-08-221-1/+1
| | | | | | | | | | The assert in r279466 checks that we call the correct version of Intrinsic::getName. The version which accepts only an ID should not be used for intrinsics with overloaded types. The global-isel code was calling the wrong version. The test CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll will ensure that we call the correct version from now on. llvm-svn: 279487
* [GraphTraits] Replace all NodeType usage with NodeRefTim Shen2016-08-221-7/+3
| | | | | | | | This should finish the GraphTraits migration. Differential Revision: http://reviews.llvm.org/D23730 llvm-svn: 279475
* [SSP] Do not set __guard_local to hidden for OpenBSD SSPTim Shen2016-08-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | __guard_local is defined as long on OpenBSD. If the source file contains a definition of __guard_local, it mismatches with the int8 pointer type used in LLVM. In that case, Module::getOrInsertGlobal() returns a cast operation instead of a GlobalVariable. Trying to set the visibility on the cast operation leads to random segfaults (seen when compiling the OpenBSD kernel, which also runs with stack protection). In the kernel, the hidden attribute does not matter. For userspace code, __guard_local is defined as hidden in the startup code. If a program re-defines __guard_local, the definition from the startup code will either win or the linker complains about multiple definitions (depending on whether the re-defined __guard_local is placed in the common segment or not). It also matches what gcc on OpenBSD does. Thanks Stefan Kempf <sisnkemp@gmail.com> for the patch! Differential Revision: http://reviews.llvm.org/D23674 llvm-svn: 279449
* Reset isUndef when removing subreg from a def operandKrzysztof Parzyszek2016-08-221-0/+2
| | | | llvm-svn: 279437
* Use SDValue::getOpcode() helper instead of via SDValue::getNode()Simon Pilgrim2016-08-201-2/+2
| | | | llvm-svn: 279381
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