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* [PM] Remove the Pass argument from all of the critical edge splittingChandler Carruth2015-01-191-4/+5
| | | | | | | | | | | | | | | | | | | APIs and replace it and numerous booleans with an option struct. The critical edge splitting API has a really large surface of flags and so it seems worth burning a small option struct / builder. This struct can be constructed with the various preserved analyses and then flags can be flipped in a builder style. The various users are now responsible for directly passing along their analysis information. This should be enough for the critical edge splitting to work cleanly with the new pass manager as well. This API is still pretty crufty and could be cleaned up a lot, but I've focused on this change just threading an option struct rather than a pass through the API. llvm-svn: 226456
* [MIScheduler] Slightly better handling of constrainLocalCopy when both ↵Michael Kuperstein2015-01-191-4/+7
| | | | | | | | | | source and dest are local This fixes PR21792. Differential Revision: http://reviews.llvm.org/D6823 llvm-svn: 226433
* std::unique_ptrify the MCStreamer argument to createAsmPrinterDavid Blaikie2015-01-182-17/+11
| | | | llvm-svn: 226414
* Improve DAG combine pass on certain IR vector patternsMehdi Amini2015-01-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector produced suboptimal code in AVX2 mode with certain IR combinations. In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32 (undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical, but then mysteriously generated rather bad code; the movq/movhpd combination didn't match. The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs would get promoted to 4f32 by the type legalizer, eventually resulting in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing these were both half the output size, concatted them and then produced a shuffle. However, the resulting concat + shuffle was more complex than it should be; in the case where the upper half of the output is undef, we probably want to generate shuffle + concat instead. This enhancement causes the vector_shuffle combine step to recognize this suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR in case the same suboptimal pattern occurs for other reasons. This results in the optimizer correctly producing the optimal movq + movhpd sequence for all three variations on this IR, even with AVX2. I've included a test case. Radar link: rdar://problem/19287012 Fix for PR 21943. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 226360
* RegisterCoalescer: Cleanup and improved comment for a subtle detail.Matthias Braun2015-01-171-6/+8
| | | | llvm-svn: 226353
* RegisterCoalescer: Cleanup by factoring out a common expressionMatthias Braun2015-01-171-5/+6
| | | | llvm-svn: 226352
* RegisterCoalescer: Cleanup comment styleMatthias Braun2015-01-171-190/+174
| | | | | | | | | | | - Consistenly put comments above the function declaration, not the definition. To achieve this some duplicate comments got merged and some comment parts describing implementation details got moved into their functions. - Consistently use doxygen comments above functions. - Do not use doxygen comments inside functions. llvm-svn: 226351
* RegisterCoalescer: Drive-by typo + whitespace fixMatthias Braun2015-01-171-2/+2
| | | | llvm-svn: 226350
* Update a commentPhilip Reames2015-01-161-1/+3
| | | | | | Be a bit more explicit about the fact that addrspace(1) is not reserved. llvm-svn: 226344
* clang-format all the GC related files (NFC)Philip Reames2015-01-169-293/+288
| | | | | | Nothing interesting here... llvm-svn: 226342
* Move ownership of GCStrategy objects to LLVMContextPhilip Reames2015-01-1612-56/+20
| | | | | | | | | | | | Note: This change ended up being slightly more controversial than expected. Chandler has tentatively okayed this for the moment, but I may be revisiting this in the near future after we settle some high level questions. Rather than have the GCStrategy object owned by the GCModuleInfo - which is an immutable analysis pass used mainly by gc.root - have it be owned by the LLVMContext. This simplifies the ownership logic (i.e. can you have two instances of the same strategy at once?), but more importantly, allows us to access the GCStrategy in the middle end optimizer. To this end, I add an accessor through Function which becomes the canonical way to get at a GCStrategy instance. In the near future, this will allows me to move some of the checks from http://reviews.llvm.org/D6808 into the Verifier itself, and to introduce optimization legality predicates for some of the recent additions to InstCombine. (These will follow as separate changes.) Differential Revision: http://reviews.llvm.org/D6811 llvm-svn: 226311
* Remove gc.root's findCustomSafePoints mechanismPhilip Reames2015-01-164-43/+10
| | | | | | | | | | | | Searching all of the existing gc.root implementations I'm aware of (all three of them), there was exactly one use of this mechanism, and that was to implement a performance improvement that should have been applied to the default lowering. Having this function is requiring a dependency on a CodeGen class (MachineFunction), in a class which is otherwise completely independent of CodeGen. I could solve this differently, but given that I see absolutely no value in preserving this mechanism, I going to just get rid of it. Note: Tis is the first time I'm intentionally breaking previously supported gc.root functionality. Given 3.6 has branched, I believe this is a good time to do this. Differential Revision: http://reviews.llvm.org/D7004 llvm-svn: 226305
* Revert r226242 - Revert Revert Don't create new comdats in CodeGenTimur Iskhodzhanov2015-01-161-5/+14
| | | | | | This breaks AddressSanitizer (ninja check-asan) on Windows llvm-svn: 226251
* Revert "Revert Don't create new comdats in CodeGen"Rafael Espindola2015-01-161-14/+5
| | | | | | | | | | | | | | | | | | This reverts commit r226173, adding r226038 back. No change in this commit, but clang was changed to also produce trivial comdats for costructors, destructors and vtables when needed. Original message: Don't create new comdats in CodeGen. This patch stops the implicit creation of comdats during codegen. Clang now sets the comdat explicitly when it is required. With this patch clang and gcc now produce the same result in pr19848. llvm-svn: 226242
* Revert "r226086 - Revert "r226071 - [RegisterCoalescer] Remove copies to ↵Hal Finkel2015-01-151-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reserved registers"" Reapply r226071 with fixes. Two fixes: 1. We need to manually remove the old and create the new 'deaf defs' associated with physical register definitions when we move the definition of the physical register from the copy point to the point of the original vreg def. This problem was picked up by the machinstr verifier, and could trigger a verification failure on test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll, so I've turned on the verifier in the tests. 2. When moving the def point of the phys reg up, we need to make sure that it is neither defined nor read in between the two instructions. We don't, however, extend the live ranges of phys reg defs to cover uses, so just checking for live-range overlap between the pair interval and the phys reg aliases won't pick up reads. As a result, we manually iterate over the range and check for reads. A test soon to be committed to the PowerPC backend will test this change. Original commit message: [RegisterCoalescer] Remove copies to reserved registers This allows the RegisterCoalescer to join "non-flipped" range pairs with a physical destination register -- which allows the RegisterCoalescer to remove copies like this: <vreg> = something (maybe a load, for example) ... (things that don't use PHYSREG) PHYSREG = COPY <vreg> (with all of the restrictions normally applied by the RegisterCoalescer: having compatible register classes, etc. ) Previously, the RegisterCoalescer handled only the opposite case (copying *from* a physical register). I don't handle the problem fully here, but try to get the common case where there is only one use of <vreg> (the COPY). An upcoming commit to the PowerPC backend will make this pattern much more common on PPC64/ELF systems. llvm-svn: 226200
* Style cleanup of old gc.root lowering codePhilip Reames2015-01-151-46/+45
| | | | | | Use static functions for helpers rather than static member functions. a) this changes the linking (minor at best), and b) this makes it obvious no object state is involved. llvm-svn: 226198
* clang-format GCStrategy.cpp & GCRootLowering.cpp (NFC)Philip Reames2015-01-152-98/+84
| | | | llvm-svn: 226196
* Split GCStrategy.cpp into two files (NFC)Philip Reames2015-01-153-380/+392
| | | | | | This preparation for an update to http://reviews.llvm.org/D6811. GCStrategy.cpp will hopefully be moving into IR/, where as the lowering logic needs to stay in CodeGen/ llvm-svn: 226195
* Revert Don't create new comdats in CodeGenTimur Iskhodzhanov2015-01-151-5/+14
| | | | | | It breaks AddressSanitizer on Windows. llvm-svn: 226173
* Fix SelectionDAG -view-*-dags filteringMehdi Amini2015-01-151-1/+1
| | | | llvm-svn: 226163
* Replace size method call of containers to empty method where appropriateAlexander Kornienko2015-01-152-3/+3
| | | | | | | | | | | | | | | | This patch was generated by a clang tidy checker that is being open sourced. The documentation of that checker is the following: /// The emptiness of a container should be checked using the empty method /// instead of the size method. It is not guaranteed that size is a /// constant-time function, and it is generally more efficient and also shows /// clearer intent to use empty. Furthermore some containers may implement the /// empty method but not implement the size method. Using empty whenever /// possible makes it easier to switch to another container in the future. Patch by Gábor Horváth! llvm-svn: 226161
* [PM] Separate the TargetLibraryInfo object from the immutable pass.Chandler Carruth2015-01-152-5/+6
| | | | | | | | | | | | | | The pass is really just a means of accessing a cached instance of the TargetLibraryInfo object, and this way we can re-use that object for the new pass manager as its result. Lots of delta, but nothing interesting happening here. This is the common pattern that is developing to allow analyses to live in both the old and new pass manager -- a wrapper pass in the old pass manager emulates the separation intrinsic to the new pass manager between the result and pass for analyses. llvm-svn: 226157
* Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"Hal Finkel2015-01-151-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reverting this while I investigate some bad behavior this is causing. As a possibly-related issue, adding -verify-machineinstrs to one of the test cases now fails because of this change: llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs *** Bad machine code: No instruction at def index *** - function: foo - basic block: BB#0 return (0x10007e21f10) [0B;736B) - liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78 4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r - register: %DS Valno #3 is defined at 624r *** Bad machine code: Live segment doesn't end at a valid instruction *** - function: foo - basic block: BB#0 return (0x10007e21f10) [0B;736B) - liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78 4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r - register: %DS [624r,624d:3) LLVM ERROR: Found 2 machine code errors. where 624r corresponds exactly to the interval combining change: 624B %RSP<def> = COPY %vreg16; GR64:%vreg16 Considering merging %vreg16 with %RSP RHS = %vreg16 [608r,624r:0) 0@608r updated: 608B %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1] Success: %vreg16 -> %RSP Result = %RSP llvm-svn: 226086
* [PM] Move TargetLibraryInfo into the Analysis library.Chandler Carruth2015-01-154-4/+4
| | | | | | | | | | | | | | | | While the term "Target" is in the name, it doesn't really have to do with the LLVM Target library -- this isn't an abstraction which LLVM targets generally need to implement or extend. It has much more to do with modeling the various runtime libraries on different OSes and with different runtime environments. The "target" in this sense is the more general sense of a target of cross compilation. This is in preparation for porting this analysis to the new pass manager. No functionality changed, and updates inbound for Clang and Polly. llvm-svn: 226078
* Win64Exception.cpp: Try to fix crash for x64 EH. "Per" might be null there.NAKAMURA Takumi2015-01-151-1/+1
| | | | llvm-svn: 226077
* [RegisterCoalescer] Remove copies to reserved registersHal Finkel2015-01-151-5/+15
| | | | | | | | | | | | | | | | | | | | | | This allows the RegisterCoalescer to join "non-flipped" range pairs with a physical destination register -- which allows the RegisterCoalescer to remove copies like this: <vreg> = something (maybe a load, for example) ... (things that don't use PHYSREG) PHYSREG = COPY <vreg> (with all of the restrictions normally applied by the RegisterCoalescer: having compatible register classes, etc. ) Previously, the RegisterCoalescer handled only the opposite case (copying *from* a physical register). I don't handle the problem fully here, but try to get the common case where there is only one use of <vreg> (the COPY). An upcoming commit to the PowerPC backend will make this pattern much more common on PPC64/ELF systems. llvm-svn: 226071
* [GC] CodeGenPrep transform: simplify offsetable relocateRamkumar Ramachandra2015-01-141-1/+155
| | | | | | | | | The transform is somewhat involved, but the basic idea is simple: find derived pointers that have been offset from the base pointer using gep and replace the relocate of the derived pointer with a gep to the relocated base pointer (with the same offset). llvm-svn: 226060
* Use MMI->getPersonality() instead of ↵Reid Kleckner2015-01-144-7/+4
| | | | | | | | | MMI->getPersonalities()[MMI->getPersonalityIndex()] Also nuke the comment about supporting multiple personalities in a single function, aka PR1414. That's just crazy. llvm-svn: 226052
* MachineVerifier: Allow undef reads if a matching superreg is defined.Matthias Braun2015-01-141-0/+19
| | | | | | | | | | | | | | | | | | | Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
* Don't create new comdats in CodeGen.Rafael Espindola2015-01-141-14/+5
| | | | | | | | | This patch stops the implicit creation of comdats during codegen. Clang now sets the comdat explicitly when it is required. With this patch clang and gcc now produce the same result in pr19848. llvm-svn: 226038
* [MBP] Add flags to disable the BadCFGConflict check in MachineBlockPlacement.Chandler Carruth2015-01-141-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | Some benchmarks have shown that this could lead to a potential performance benefit, and so adding some flags to try to help measure the difference. A possible explanation. In diamond-shaped CFGs (A followed by either B or C both followed by D), putting B and C both in between A and D leads to the code being less dense than it could be. Always either B or C have to be skipped increasing the chance of cache misses etc. Moving either B or C to after D might be beneficial on average. In the long run, but we should probably do a better job of analyzing the basic block and branch probabilities to move the correct one of B or C to after D. But even if we don't use this in the long run, it is a good baseline for benchmarking. Original patch authored by Daniel Jasper with test tweaks and a second flag added by me. Differential Revision: http://reviews.llvm.org/D6969 llvm-svn: 226034
* Emit the Itanium LSDA for unknown EH personalities on Win64Reid Kleckner2015-01-142-11/+10
| | | | | | | | | | This fixes lots of generic CodeGen tests that use __gcc_personality_v0. This suggests that using ExceptionHandling::MSVC was a mistake, and we should instead classify each function by personality function. This would, for example, allow us to LTO a binary containing uses of SEH and Itanium EH. llvm-svn: 226019
* Remove dead code for llvm.eh.selector in the old EH modelReid Kleckner2015-01-141-54/+0
| | | | llvm-svn: 226018
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-1431-45/+32
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* SelectionDAG: add a -filter-view-dags option to llcMehdi Amini2015-01-141-10/+25
| | | | | | | | | This option takes the name of the basic block you want to visualize with -view-*-dags Differential Revision: http://reviews.llvm.org/D6948 llvm-svn: 225953
* DAG Combiner: Fold SelectCC When Cond is UNDEFMehdi Amini2015-01-141-4/+7
| | | | | | | | | In case folding a node end up with a NaN as operand for the select, the folding of the condition of the selectcc node returns "UNDEF". Differential Revision: http://reviews.llvm.org/D6889 llvm-svn: 225952
* Add assertions for out of bound index in ComputeLinearIndexMehdi Amini2015-01-141-2/+3
| | | | llvm-svn: 225951
* Fold a loop for array processing in ComputeLinearIndexMehdi Amini2015-01-141-8/+13
| | | | | | | | | | When processing an array, every Elt has the same layout, it is useless to recursively call each ComputeLinearIndex on each element. Just do it once and multiply by the number of elements. Differential Revision: http://reviews.llvm.org/D6832 llvm-svn: 225949
* Revert "Insert random noops to increase security against ROP attacks (llvm)"JF Bastien2015-01-144-106/+0
| | | | | | | This reverts commit: http://reviews.llvm.org/D3392 llvm-svn: 225948
* Implement new way of expanding extloads.Matt Arsenault2015-01-142-16/+19
| | | | | | | | | | | | | | | Now that the source and destination types can be specified, allow doing an expansion that doesn't use an EXTLOAD of the result type. Try to do a legal extload to an intermediate type and extend that if possible. This generalizes the special case custom lowering of extloads R600 has been using to work around this problem. This also happens to fix a bug that would incorrectly use more aligned loads than should be used. llvm-svn: 225925
* Insert random noops to increase security against ROP attacks (llvm)JF Bastien2015-01-144-0/+106
| | | | | | | | | | | | | | | | | | | | A pass that adds random noops to X86 binaries to introduce diversity with the goal of increasing security against most return-oriented programming attacks. Command line options: -noop-insertion // Enable noop insertion. -noop-insertion-percentage=X // X% of assembly instructions will have a noop prepended (default: 50%, requires -noop-insertion) -max-noops-per-instruction=X // Randomly generate X noops per instruction. ie. roll the dice X times with probability set above (default: 1). This doesn't guarantee X noop instructions. In addition, the following 'quick switch' in clang enables basic diversity using default settings (currently: noop insertion and schedule randomization; it is intended to be extended in the future). -fdiversify This is the llvm part of the patch. clang part: D3393 http://reviews.llvm.org/D3392 Patch by Stephen Crane (@rinon) llvm-svn: 225908
* Adjust ScheduleDAGSDNodes::RegDefIter for patchpointsHal Finkel2015-01-141-0/+8
| | | | | | | | | | | | | | | PATCHPOINT is a strange pseudo-instruction. Depending on how it is used, and whether or not the AnyReg calling convention is being used, it might or might not define a value. However, its TableGen definition says that it defines one value, and so when it doesn't, the code in ScheduleDAGSDNodes::RegDefIter becomes confused and the code that uses the RegDefIter will try to get the register class of the MVT::Other type associated with the PATCHPOINT's chain result (under certain circumstances). This will be covered by the PPC64 PatchPoint test cases once that support is re-committed. llvm-svn: 225907
* CodeGen support for x86_64 SEH catch handlers in LLVMReid Kleckner2015-01-149-18/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds handling for ExceptionHandling::MSVC, used by the x86_64-pc-windows-msvc triple. It assumes that filter functions have already been outlined in either the frontend or the backend. Filter functions are used in place of the landingpad catch clause type info operands. In catch clause order, the first filter to return true will catch the exception. The C specific handler table expects the landing pad to be split into one block per handler, but LLVM IR uses a single landing pad for all possible unwind actions. This patch papers over the mismatch by synthesizing single instruction BBs for every catch clause to fill in the EH selector that the landing pad block expects. Missing functionality: - Accessing data in the parent frame from outlined filters - Cleanups (from __finally) are unsupported, as they will require outlining and parent frame access - Filter clauses are unsupported, as there's no clear analogue in SEH In other words, this is the minimal set of changes needed to write IR to catch arbitrary exceptions and resume normal execution. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D6300 llvm-svn: 225904
* Debug Info: Implement DwarfCompileUnit::addComplexAddress() usingAdrian Prantl2015-01-141-47/+14
| | | | | | | | DIEDwarfExpression (and get rid of a bunch of redundant code). NFC llvm-svn: 225900
* Debug Info: Emitting a register in DwarfExpression may fail. Report theAdrian Prantl2015-01-143-16/+26
| | | | | | | | status in a bool and let the users deal with the error. NFC. llvm-svn: 225899
* Debug Info: Move DIEDwarfExpression into DwarfExpression.h because itAdrian Prantl2015-01-142-14/+17
| | | | | | | | needs to be accessed from both DwarfCompileUnit.cpp and DwarfUnit.cpp. NFC. llvm-svn: 225898
* Migrate ABIName to MCTargetOptions so that it can be shared betweenEric Christopher2015-01-141-7/+0
| | | | | | the TargetMachine level and the MC level. llvm-svn: 225891
* Debug Info: Don't bother emitting DW_AT_frame_base if the function hasAdrian Prantl2015-01-141-1/+2
| | | | | | no frame register. "Tested" via an assertion triggered by DwarfExpression. llvm-svn: 225858
* Revert "Debug Info: Bail out of AddMachineRegPiece() if MachineReg is not a"Adrian Prantl2015-01-141-6/+0
| | | | | | | | | This reverts commit r225852, it was a bad idea. MachineReg should always be a physical register. If it isn't this DebugLoc shouldn't have been created in the first place. llvm-svn: 225857
* Debug Info: Bail out of AddMachineRegPiece() if MachineReg is not aAdrian Prantl2015-01-131-0/+6
| | | | | | | physical register. The call to getMinimalPhysRegClass() later on asserts on this condition. llvm-svn: 225852
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