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| author | Hal Finkel <hfinkel@anl.gov> | 2015-01-15 03:08:59 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-01-15 03:08:59 +0000 |
| commit | dd669615dd604f5ac4d89c6c062cd8a7bf345f38 (patch) | |
| tree | 4b380886020511990c02cf836d366aaea6d880fa /llvm/lib/CodeGen | |
| parent | 103f309504bb208dbbf96ba0287aa4e3a871277d (diff) | |
| download | bcm5719-llvm-dd669615dd604f5ac4d89c6c062cd8a7bf345f38.tar.gz bcm5719-llvm-dd669615dd604f5ac4d89c6c062cd8a7bf345f38.zip | |
Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Reverting this while I investigate some bad behavior this is causing. As a
possibly-related issue, adding -verify-machineinstrs to one of the test cases
now fails because of this change:
llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs
*** Bad machine code: No instruction at def index ***
- function: foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register: %DS
Valno #3 is defined at 624r
*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function: foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register: %DS
[624r,624d:3)
LLVM ERROR: Found 2 machine code errors.
where 624r corresponds exactly to the interval combining change:
624B %RSP<def> = COPY %vreg16; GR64:%vreg16
Considering merging %vreg16 with %RSP
RHS = %vreg16 [608r,624r:0) 0@608r
updated: 608B %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1]
Success: %vreg16 -> %RSP
Result = %RSP
llvm-svn: 226086
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RegisterCoalescer.cpp | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 517bc2dbe12..b8cae4a59ed 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -1209,10 +1209,10 @@ bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) { } LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg()); - if (JoinVInt.containsOneValue()) + if (CP.isFlipped() && JoinVInt.containsOneValue()) return true; - DEBUG(dbgs() << "\tCannot join complex intervals into reserved register.\n"); + DEBUG(dbgs() << "\tCannot join defs into reserved register.\n"); return false; } @@ -1431,7 +1431,8 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { LiveInterval &RHS = LIS->getInterval(CP.getSrcReg()); DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n'); - assert(RHS.containsOneValue() && "Invalid join with reserved register"); + assert(CP.isFlipped() && RHS.containsOneValue() && + "Invalid join with reserved register"); // Optimization for reserved registers like ESP. We can only merge with a // reserved physreg if RHS has a single value that is a copy of CP.DstReg(). @@ -1452,18 +1453,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // defs are there. // Delete the identity copy. - MachineInstr *CopyMI; - if (CP.isFlipped()) { - CopyMI = MRI->getVRegDef(RHS.reg); - } else { - if (!MRI->hasOneNonDBGUse(RHS.reg)) { - DEBUG(dbgs() << "\t\tMultiple vreg uses\n"); - return false; - } - - CopyMI = &*MRI->use_instr_nodbg_begin(RHS.reg); - } - + MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg); LIS->RemoveMachineInstrFromMaps(CopyMI); CopyMI->eraseFromParent(); |

