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* GlobalISel: translate floating-point comparisonsTim Northover2016-08-192-11/+29
| | | | llvm-svn: 279319
* GlobalISel: translate floating-point constantsTim Northover2016-08-192-0/+7
| | | | llvm-svn: 279311
* GlobalISel: support translating select instructions.Tim Northover2016-08-192-0/+17
| | | | llvm-svn: 279309
* GlobalISel: fix insert/extract to work on ConstantExprs too.Tim Northover2016-08-191-18/+27
| | | | | | | No tests yet unfortunately (ConstantFolding reduces all supported constants to ConstantInts before we get to translation). Soon. llvm-svn: 279308
* GlobalISel: translate insertvalue instructions.Tim Northover2016-08-191-0/+24
| | | | | | | | | | This adds a G_INSERT instruction, which technically makes G_SEQUENCE redundant (it's equivalent to a G_INSERT into an IMPLICIT_DEF). We'll leave G_SEQUENCE for now though: it's likely to be far more common as it's a fundamental part of legalization, so avoiding the mess and bloat of the extra IMPLICIT_DEFs is probably worthwhile. llvm-svn: 279306
* MachineScheduler: Add constructor functions for the DAGMutationsTom Stellard2016-08-191-4/+40
| | | | | | | | | | | | Summary: This way they can be re-used by target-specific schedulers. Reviewers: atrick, MatzeB, kparzysz Subscribers: kparzysz, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D23678 llvm-svn: 279305
* GlobalISel: improve representation of G_SEQUENCE and G_EXTRACTTim Northover2016-08-193-20/+42
| | | | | | | | | | | | First, make sure all types involved are represented, rather than being implicit from the register width. Second, canonicalize all types to scalar. These operations just act in bits and don't care about vectors. Also standardize spelling of Indices in the MachineIRBuilder (NFC here). llvm-svn: 279294
* Revert "IfConversion: Rescan diamonds."Kyle Butt2016-08-191-115/+34
| | | | | | This reverts commit bfd62a4b4465dd21811bf615c3b04c30ddb09f7b. llvm-svn: 279289
* Revert "CodeGen: If Convert blocks that would form a diamond when tail-merged."Kyle Butt2016-08-191-287/+78
| | | | | | This reverts commit 0fda93481c4231c06b838ef476c0c404c51ff875. llvm-svn: 279288
* GlobalISel: allow extractvalue to extract an aggregate.Tim Northover2016-08-191-1/+1
| | | | llvm-svn: 279287
* GlobalISel: support translation of extractvalue instructions.Tim Northover2016-08-193-2/+23
| | | | llvm-svn: 279285
* GlobalISel: support overflow arithmetic intrinsics.Tim Northover2016-08-193-15/+63
| | | | | | | | | | | | Unsigned addition and subtraction can reuse the instructions created to legalize large width operations (i.e. both produce and consume a carry flag). Signed operations and multiplies get a dedicated op-with-overflow instruction. Once this is produced the two values are combined into a struct register (which will almost always be merged with a corresponding G_EXTRACT as part of legalization). llvm-svn: 279278
* [CodeGen] Fix a trivial type conversion bug dating back to pre-2008James Molloy2016-08-191-1/+1
| | | | | | | | The heuristic above this code is incredibly suspect, but disregarding that it mutates the cast opcode so we need to check the *mutated* opcode later to see if we need to emit an AssertSext or AssertZext node. Fixes PR29041. llvm-svn: 279223
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-08-194-347/+165
| | | | | | | | | | | The ppc64 multistage bot fails on this. This reverts commit r279124. Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change This reverts commit r279171. llvm-svn: 279199
* CodeGen: Add/Factor out LiveRegUnits class; NFCIMatthias Braun2016-08-183-60/+107
| | | | | | | | | | | | | This is a set of register units intended to track register liveness, it is similar in spirit to LivePhysRegs. You can also think of this as the liveness tracking parts of the RegisterScavenger factored out into an own class. This was proposed in http://llvm.org/PR27609 Differential Revision: http://reviews.llvm.org/D21916 llvm-svn: 279171
* CodeGen: If Convert blocks that would form a diamond when tail-merged.Kyle Butt2016-08-181-78/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following function currently relies on tail-merging for if conversion to succeed. The common tail of cond_true and cond_false is extracted, and this then forms a diamond pattern that can be successfully if converted. If this block does not get extracted, either because tail-merging is disabled or the threshold is higher, we should still recognize this pattern and if-convert it. Fixed a regression in the original commit. Need to un-reverse branches after reversing them, or other conversions go awry. Regression on self-hosting bots with no obvious explanation. Tidied up range handling to be more obviously correct, but there was no smoking gun. define i32 @t2(i32 %a, i32 %b) nounwind { entry: %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] br i1 %tmp1434, label %bb17, label %bb.outer bb.outer: ; preds = %cond_false, %entry %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] br label %bb bb: ; preds = %cond_true, %bb.outer %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] %tmp. = sub i32 0, %b_addr.021.0.ph %tmp.40 = mul i32 %indvar, %tmp. %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph br i1 %tmp3, label %cond_true, label %cond_false cond_true: ; preds = %bb %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph %indvar.next = add i32 %indvar, 1 br i1 %tmp1437, label %bb17, label %bb cond_false: ; preds = %bb %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 br i1 %tmp14, label %bb17, label %bb.outer bb17: ; preds = %cond_false, %cond_true, %entry %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ret i32 %a_addr.026.1 } Without tail-merging or diamond-tail if conversion: LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ble LBB1_3 @ BB#2: @ %cond_true @ in Loop: Header=BB1_1 Depth=1 subs r0, r0, r1 cmp r1, r0 it ne cmpne r0, r1 bgt LBB1_4 LBB1_3: @ %cond_false @ in Loop: Header=BB1_1 Depth=1 subs r1, r1, r0 cmp r1, r0 bne LBB1_1 LBB1_4: @ %bb17 bx lr With diamond-tail if conversion, but without tail-merging: @ BB#0: @ %entry cmp r0, r1 it eq bxeq lr LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ite le suble r1, r1, r0 subgt r0, r0, r1 cmp r1, r0 bne LBB1_1 @ BB#2: @ %bb17 bx lr llvm-svn: 279168
* IfConversion: Rescan diamonds.Kyle Butt2016-08-181-34/+115
| | | | | | | | | | | The cost of predicating a diamond is only the instructions that are not shared between the two branches. Additionally If a predicate clobbering instruction occurs in the shared portion of the branches (e.g. a cond move), it may still be possible to if convert the sub-cfg. This change handles these two facts by rescanning the non-shared portion of a diamond sub-cfg to recalculate both the predication cost and whether both blocks are pred-clobbering. llvm-svn: 279167
* IfConversion: Handle inclusive ranges more carefully.Kyle Butt2016-08-181-22/+56
| | | | | | | | | | | This may affect calculations for thresholds, but is not a significant change in behavior. The problem was that an inclusive range must have an additonal flag to showr that it is empty, because otherwise begin == end implies that the range has one element, and it may not be possible to move past on either side. llvm-svn: 279166
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-08-182-108/+243
| | | | | | | | | | | | | | | | Re-apply r276044 with off-by-1 instruction fix for the reload placement. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 279124
* Branch Folding: Accept explicit threshold for tail merge size.Kyle Butt2016-08-183-22/+44
| | | | | | | | This is prep work for allowing the threshold to be different during layout, and to enforce a single threshold between merging and duplicating during layout. No observable change intended. llvm-svn: 279117
* (Trivial) TargetPassConfig: assert when TargetMachine has no MCAsmInfoAlex Bradbury2016-08-181-1/+3
| | | | | | | | | | | | | | | Summary: This is a pretty trivial, but I thought it was worth just checking that nobody feels it's completely the wrong thing to be doing. The motivation is that when starting a new backend, you often start with a minimal stub, pretty much just FooTargetMachine and FooTargetInfo. Once that's built, you might naturally try `llc -march=foo myinput.ll` and it seems more developer-friendly if this ends up asserting due to the lack of MCAsmInfo with an informative message rather than just segfaulting. Reviewers: MatzeB, chandlerc Subscribers: bogner, llvm-commits Differential Revision: https://reviews.llvm.org/D23443 llvm-svn: 279061
* TailDuplicator: Fix crash after r278974Matthias Braun2016-08-181-1/+1
| | | | | | | | Some inputs would after r278974 without this fix (see http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_build/2733/console for an example) llvm-svn: 279022
* Tail Duplication: Accept explicit threshold for duplicating.Kyle Butt2016-08-171-4/+8
| | | | | | | | This will allow tail duplication and tail merging during layout to have a shared threshold to make sure that they don't overlap. No observable change intended. llvm-svn: 278981
* TailDuplicator: Use optForSize instead of hasFnAttribute.Kyle Butt2016-08-171-1/+1
| | | | | | | This will cause minsize functions to have the same threshold as optsize functions, but otherwise should have no effects. llvm-svn: 278980
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1710-38/+37
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-177-1/+106
| | | | llvm-svn: 278969
* [GraphWriter] Change GraphWriter to use NodeRef in GraphTraitsTim Shen2016-08-171-0/+1
| | | | | | | | | | | | | | | Summary: This is part of the "NodeType* -> NodeRef" migration. Notice that since GraphWriter prints object address as identity, I added a static_assert on NodeRef to be a pointer type. Reviewers: dblaikie Subscribers: llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D23580 llvm-svn: 278966
* Fix for PR29010Marina Yatsina2016-08-171-1/+5
| | | | | | | | | | | This is a fix for https://llvm.org/bugs/show_bug.cgi?id=29010 Root cause of the bug is that the register class of the machine instruction operand does not fully reflect if this registers that can be allocated. Both for i386 and x86_64 the operand's register class is VR128RegClass and thus contains xmm0-xmm15, though in i386 we can only use xmm0-xmm8. In order to get the actual allocable registers of the class we need to use RegisterClassInfo. Differential Revision: https://reviews.llvm.org/D23613 llvm-svn: 278954
* Support the DW_AT_noreturn DWARF flag.Adrian Prantl2016-08-171-0/+3
| | | | | | | | | | | This is used to mark functions with the C++11 [[ noreturn ]] or C11 _Noreturn attributes. Patch by Victor Leschuk! https://reviews.llvm.org/D23167 llvm-svn: 278940
* Fixing bug committed in rev. 278321Marina Yatsina2016-08-171-3/+6
| | | | | | | | | | In theory the indices of RC (and thus the index used for LiveRegs) may differ from the indices of OpRC. Fixed the code to extract the correct RC index. OpRC contains the first X consecutive elements of RC, and thus their indices are currently de facto the same, therefore a test cannot be added at this point. Differential Revision: https://reviews.llvm.org/D23491 llvm-svn: 278923
* Fix bug in DAGBuilder for getelementptr with expanded vector.Ayman Musa2016-08-171-1/+2
| | | | | | | Replacing the usage of MVT with EVT in case the vector type is expanded. Differential Revision: https://reviews.llvm.org/D23306 llvm-svn: 278913
* First commit (test commit) - Adding empty line.Ayman Musa2016-08-171-0/+1
| | | | llvm-svn: 278910
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-176-8/+9
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* IfConversion: Use references instead of pointers where possible; NFCMatthias Braun2016-08-171-124/+134
| | | | | | Also put some commonly used subexpressions into variables. llvm-svn: 278895
* IfConversion: Use range based for; NFCMatthias Braun2016-08-171-35/+23
| | | | | | | | Also avoid some pointless use of auto! Because that's friendlier to readers and avoids several types accidentally resolving to unnecessary references here (MachineInstr *&, unsigned &). llvm-svn: 278894
* IfConversion: Improve doxygen commentsMatthias Braun2016-08-171-63/+46
| | | | llvm-svn: 278893
* CodeGen: Avoid dereferencing end() in OptimizePHIs::OptimizeBBDuncan P. N. Exon Smith2016-08-171-1/+1
| | | | llvm-svn: 278879
* CodeGen: Avoid dereferencing end() when unconstifying iteratorsDuncan P. N. Exon Smith2016-08-161-8/+4
| | | | | | | | Rather than doing a funny dance that relies on dereferencing end() not crashing, add some API to MachineInstrBundleIterator to get a non-const version of the iterator. llvm-svn: 278870
* Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough.Kyle Butt2016-08-161-0/+10
| | | | | | | | | | | | If AnalyzeBranch can't analyze a block and it is possible to fallthrough, then duplicating the block doesn't make sense, as only one block can be the layout predecessor for the un-analyzable fallthrough. Submitted wit a test case, but NOTE: the test case doesn't currently fail. However, the test case fails with D20505 and would have saved me some time debugging. llvm-svn: 278866
* CodeGen: Don't dereference end() in MachineBasicBlock::CorrectExtraCFGEdgesDuncan P. N. Exon Smith2016-08-161-4/+4
| | | | | | | | The current MachineBasicBlock might be the last block, so FallThru may be past the end(). Use getNextNode(), which will convert to nullptr, rather than &*++, which is invalid if we reach the end(). llvm-svn: 278858
* TailDuplicator: Use range loopsMatt Arsenault2016-08-161-42/+23
| | | | llvm-svn: 278847
* [MBP] do not reorder and move up loop latch blockSjoerd Meijer2016-08-161-0/+10
| | | | | | | | | | Do not reorder and move up a loop latch block before a loop header when optimising for size because this will generate an extra unconditional branch. Differential Revision: https://reviews.llvm.org/D22521 llvm-svn: 278840
* When the inline spiller rematerializes an instruction, take the debug ↵Wolfgang Pieb2016-08-161-1/+7
| | | | | | | | | | | | location from the instruction that immediately follows the rematerialization point. Patch by Andrea DiBiagio. Differential Revision: http://reviews.llvm.org/D23539 llvm-svn: 278822
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+4
| | | | llvm-svn: 278810
* [Pipeliner] Fix an asssert due to invalid Phi in the epilogBrendon Cahoon2016-08-161-2/+1
| | | | | | | | | | | | The pipeliner was generating an invalid Phi name for an operand in the epilog block, which caused an assert in the live variable analysis pass. The fix is to the code that generates new Phis in the epilog block. In this case, there is an existing Phi that needs to be reused rather than creating a new Phi instruction. Differential Revision: https://reviews.llvm.org/D23513 llvm-svn: 278805
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-161-2/+2
| | | | | | And mark it as legal. llvm-svn: 278802
* [x86] Refactor a PowerPC specific ctlz/srl transformation (NFC).Pierre Gousseau2016-08-161-0/+25
| | | | | | | | Following the discussion on D22038, this refactors a PowerPC specific setcc -> srl(ctlz) transformation so it can be used by other targets. Differential Revision: https://reviews.llvm.org/D23445 llvm-svn: 278799
* [ADT] Change PostOrderIterator to use NodeRef. NFC.Tim Shen2016-08-151-3/+4
| | | | | | | | | | Reviewers: dblaikie Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D23522 llvm-svn: 278752
* Fix typo in lowering for fp128 ueq.Eli Friedman2016-08-151-1/+1
| | | | | | | | Regression from r259791. Differential Revision: https://reviews.llvm.org/D23374 llvm-svn: 278750
* GlobalISel: support loads and stores of strange types.Tim Northover2016-08-152-11/+15
| | | | | | | Before we mischaracterized structs and i1 types as a scalar with size 0 in various ways. llvm-svn: 278744
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