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* Remove unused but set variables.Benjamin Kramer2011-06-182-19/+4
| | | | llvm-svn: 133347
* Fix UMULO support for 2x register width to allow the fullEric Christopher2011-06-181-0/+21
| | | | | | | | | range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 llvm-svn: 133318
* Only call TRI::getRawAllocationOrder to resolve a target-dependent hint.Jakob Stoklund Olesen2011-06-171-2/+6
| | | | llvm-svn: 133313
* Fix comment.Eric Christopher2011-06-171-2/+1
| | | | llvm-svn: 133307
* Use the verbose asm flag instead of a new flag for decoding the LSDA.Bill Wendling2011-06-171-4/+1
| | | | llvm-svn: 133292
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-173-4/+71
| | | | | | | | | calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
* Add an option that allows one to "decode" the LSDA.Bill Wendling2011-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LSDA is a bit difficult for the non-initiated to read. Even with comments, it's not always clear what's going on. This wraps the ASM streamer in a class that retains the LSDA and then emits a human-readable description of what's going on in it. So instead of having to make sense of: Lexception1: .byte 255 .byte 155 .byte 168 .space 1 .byte 3 .byte 26 Lset0 = Ltmp7-Leh_func_begin1 .long Lset0 Lset1 = Ltmp812-Ltmp7 .long Lset1 Lset2 = Ltmp913-Leh_func_begin1 .long Lset2 .byte 3 Lset3 = Ltmp812-Leh_func_begin1 .long Lset3 Lset4 = Leh_func_end1-Ltmp812 .long Lset4 .long 0 .byte 0 .byte 1 .byte 0 .byte 2 .byte 125 .long __ZTIi@GOTPCREL+4 .long __ZTIPKc@GOTPCREL+4 you can read this instead: ## Exception Handling Table: Lexception1 ## @LPStart Encoding: omit ## @TType Encoding: indirect pcrel sdata4 ## @TType Base: 40 bytes ## @CallSite Encoding: udata4 ## @Action Table Size: 26 bytes ## Action 1: ## A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception. ## For type(s): __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4 ## Action 2: ## A throw between Ltmp812 and Leh_func_end1 does not have a landing pad. llvm-svn: 133286
* getSuccWeight returns now default 0 if Weights vector is empty.Jakub Staszak2011-06-171-2/+4
| | | | llvm-svn: 133271
* Allow empty Weights vector.Jakub Staszak2011-06-171-1/+2
| | | | llvm-svn: 133265
* Two fixes relating to debug value:Rafael Espindola2011-06-171-0/+10
| | | | | | | | * We should change the generated code because of a debug use. * Avoid creating debug uses of undef, as they become a kill. Test to follow. llvm-svn: 133255
* Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to ↵Lang Hames2011-06-171-4/+9
| | | | | | PBQP allocation. Patch by Arnaud Allard de Grandmaison. llvm-svn: 133249
* Enable early duplication of small blocks. There are still improvements toRafael Espindola2011-06-171-29/+32
| | | | | | be made, but this is already a win. llvm-svn: 133240
* Rename TRI::getAllocationOrder() to getRawAllocationOrder().Jakob Stoklund Olesen2011-06-162-17/+15
| | | | | | | | | | | Also switch the return type to ArrayRef<unsigned> which works out nicely for ARM's implementation of this function because of the clever ArrayRef constructors. The name change indicates that the returned allocation order may contain reserved registers as has been the case for a while. llvm-svn: 133216
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-165-33/+39
| | | | | | No functional change was intended. llvm-svn: 133202
* Move PBQP off allocation_order_begin. No functional change intended.Jakob Stoklund Olesen2011-06-161-5/+4
| | | | | | | I think PBQP could use RegisterClassInfo, but it didn't fit neatly with the external interfaces that PBQP uses, so I'll leave that to Lang. llvm-svn: 133186
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-166-18/+233
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-161-5/+6
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Switch linear scan to using RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-18/+12
| | | | | | | | | This avoids the manual filtering of reserved registers and removes the dependency on allocation_order_begin(). Palliative care... llvm-svn: 133177
* Test commit.Jakub Staszak2011-06-161-7/+7
| | | | llvm-svn: 133174
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-163-18/+21
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-161-61/+109
| | | | llvm-svn: 133124
* Function::getNumBlockIDs() should be used instead of Function::size() to set ↵Anna Zaks2011-06-161-1/+1
| | | | | | the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix). llvm-svn: 133113
* The ARC language-specific optimizer. Credit to Dan Gohman.John McCall2011-06-151-0/+4
| | | | llvm-svn: 133108
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-152-9/+47
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. llvm-svn: 133106
* Handle jump tables. Test to follow soon.Rafael Espindola2011-06-151-0/+2
| | | | llvm-svn: 133083
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-153-15/+55
| | | | | | Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
* getZeroExtendInReg needs to get a scalar typeNadav Rotem2011-06-151-1/+2
| | | | llvm-svn: 133057
* Enable the simplification of truncating-store after fixing the usage ofNadav Rotem2011-06-152-4/+5
| | | | | | | | GetDemandBits (which must operate on the vector element type). Fix the a usage of getZeroExtendInReg which must also be done on scalar types. llvm-svn: 133052
* When pattern matching during instruction selection make sure shl x,1 is notChad Rosier2011-06-141-0/+3
| | | | | | | | converted to add x,x if x is a undef. add undef, undef does not guarantee that the resulting low order bit is zero. Fixes <rdar://problem/9453156> and <rdar://problem/9487392>. llvm-svn: 133022
* Revert r133004 ; it's breaking nightly tests.Eli Friedman2011-06-141-4/+21
| | | | llvm-svn: 133007
* Partial revert of 132882.Rafael Espindola2011-06-141-21/+4
| | | | | | | | | | | | | | | | Dan noted that this would work on the case shown on the commit message. I think the case that was failing was a bb ending with a redundant conditional jump: ... jne foo foo: ... I was unable to find any such case in the tests or in a debug build of clang, so I will revert this part of the patch and watch the bots. llvm-svn: 133004
* Add 132986 back, but avoid non-determinism if a bb address gets reused.Rafael Espindola2011-06-142-5/+26
| | | | llvm-svn: 132995
* revert 132986 to see if the bots go green.Rafael Espindola2011-06-142-23/+5
| | | | llvm-svn: 132988
* Add a testcase for checking the integer-promotion of many different vectorNadav Rotem2011-06-142-2/+171
| | | | | | | | | | | | | types (with power of two types such as 8,16,32 .. 512). Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding only if the target of the conversion is an integer (when the type action is scalarize). Add handling to the legalization of vector load/store in cases where the saved vector is integer-promoted. llvm-svn: 132985
* Disable trunc-store simplification on vectors.Nadav Rotem2011-06-141-1/+1
| | | | llvm-svn: 132984
* Implement Jakob's suggestion on how to detect fall thought without callingRafael Espindola2011-06-141-12/+19
| | | | | | AnalyzeBranch. llvm-svn: 132981
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+3
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
* Make the threshold used by branch folding softer. Before we would get aRafael Espindola2011-06-142-5/+23
| | | | | | | sharp all or nothing transition when one extra predecessor was added. Now we still test first ones for merging. llvm-svn: 132974
* Fix a bug in FindMemType. When widening vector loads, use a wider memory typeNadav Rotem2011-06-131-0/+2
| | | | | | | only if the number of packed elements is a power of two. Bug found in Duncan's testcase. llvm-svn: 132923
* Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen2011-06-131-7/+5
| | | | | | | | | | In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. llvm-svn: 132900
* Include callee-saved registers in debug output.Jakob Stoklund Olesen2011-06-131-1/+1
| | | | llvm-svn: 132899
* Fix invalid uses of Twine. Hopefully this fixes the problem that Takumi isRafael Espindola2011-06-131-7/+7
| | | | | | having. llvm-svn: 132898
* Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem2011-06-121-5/+17
| | | | | | types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
* Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem2011-06-121-21/+20
| | | | | | | | | Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). llvm-svn: 132892
* Really fix the fall-through logic.Rafael Espindola2011-06-121-0/+3
| | | | | | Add a triple to the tests. llvm-svn: 132885
* Fix silly bug I introduce in the previous commit. Fixes debug builds.Rafael Espindola2011-06-121-3/+3
| | | | llvm-svn: 132883
* AnalyzeBranch doesn't change which successors a bb has, just the orderRafael Espindola2011-06-121-4/+11
| | | | | | | | | | | | | | | | | | we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- llvm-svn: 132882
* Revert r132871.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132872
* Typo.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132871
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